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| author | 2014-05-18 22:50:41 +0200 | |
|---|---|---|
| committer | 2014-06-12 06:10:54 -0400 | |
| commit | 4c2bff61e5e8409cd25a5db396ce3574486f94b1 (patch) | |
| tree | 39110e36491ec9c6b3e938b7c2223b33fc3db5b5 /src/video_core | |
| parent | Further refine GPU command list debugging. (diff) | |
| download | yuzu-4c2bff61e5e8409cd25a5db396ce3574486f94b1.tar.gz yuzu-4c2bff61e5e8409cd25a5db396ce3574486f94b1.tar.xz yuzu-4c2bff61e5e8409cd25a5db396ce3574486f94b1.zip | |
Pica: Use some template magic to define register structures efficiently.
Diffstat (limited to 'src/video_core')
| -rw-r--r-- | src/video_core/pica.h | 127 |
1 files changed, 102 insertions, 25 deletions
diff --git a/src/video_core/pica.h b/src/video_core/pica.h index 7cbc45f98..f0fa3aba9 100644 --- a/src/video_core/pica.h +++ b/src/video_core/pica.h | |||
| @@ -9,45 +9,122 @@ | |||
| 9 | 9 | ||
| 10 | #include "common/bit_field.h" | 10 | #include "common/bit_field.h" |
| 11 | #include "common/common_types.h" | 11 | #include "common/common_types.h" |
| 12 | #include "common/register_set.h" | ||
| 12 | 13 | ||
| 13 | namespace Pica { | 14 | namespace Pica { |
| 14 | 15 | ||
| 15 | enum class CommandId : u32 | 16 | struct Regs { |
| 16 | { | 17 | enum Id : u32 { |
| 17 | ViewportSizeX = 0x41, | 18 | ViewportSizeX = 0x41, |
| 18 | ViewportInvSizeX = 0x42, | 19 | ViewportInvSizeX = 0x42, |
| 19 | ViewportSizeY = 0x43, | 20 | ViewportSizeY = 0x43, |
| 20 | ViewportInvSizeY = 0x44, | 21 | ViewportInvSizeY = 0x44, |
| 21 | ViewportCorner = 0x68, | 22 | ViewportCorner = 0x68, |
| 22 | DepthBufferFormat = 0x116, | 23 | DepthBufferFormat = 0x116, |
| 23 | ColorBufferFormat = 0x117, | 24 | ColorBufferFormat = 0x117, |
| 24 | DepthBufferAddress = 0x11C, | 25 | DepthBufferAddress = 0x11C, |
| 25 | ColorBufferAddress = 0x11D, | 26 | ColorBufferAddress = 0x11D, |
| 26 | ColorBufferSize = 0x11E, | 27 | ColorBufferSize = 0x11E, |
| 28 | |||
| 29 | VertexArrayBaseAddr = 0x200, | ||
| 30 | VertexDescriptor = 0x201, // 0x202 | ||
| 31 | VertexAttributeOffset = 0x203, // 0x206,0x209,0x20C,0x20F,0x212,0x215,0x218,0x21B,0x21E,0x221,0x224 | ||
| 32 | VertexAttributeInfo0 = 0x204, // 0x207,0x20A,0x20D,0x210,0x213,0x216,0x219,0x21C,0x21F,0x222,0x225 | ||
| 33 | VertexAttributeInfo1 = 0x205, // 0x208,0x20B,0x20E,0x211,0x214,0x217,0x21A,0x21D,0x220,0x223,0x226 | ||
| 34 | |||
| 35 | NumIds = 0x300, | ||
| 36 | }; | ||
| 37 | |||
| 38 | template<Id id> | ||
| 39 | union Struct; | ||
| 27 | }; | 40 | }; |
| 28 | 41 | ||
| 42 | static inline Regs::Id VertexAttributeOffset(int n) | ||
| 43 | { | ||
| 44 | return static_cast<Regs::Id>(0x203 + 3*n); | ||
| 45 | } | ||
| 46 | |||
| 47 | static inline Regs::Id VertexAttributeInfo0(int n) | ||
| 48 | { | ||
| 49 | return static_cast<Regs::Id>(0x204 + 3*n); | ||
| 50 | } | ||
| 51 | |||
| 52 | static inline Regs::Id VertexAttributeInfo1(int n) | ||
| 53 | { | ||
| 54 | return static_cast<Regs::Id>(0x205 + 3*n); | ||
| 55 | } | ||
| 56 | |||
| 29 | union CommandHeader { | 57 | union CommandHeader { |
| 30 | CommandHeader(u32 h) : hex(h) {} | 58 | CommandHeader(u32 h) : hex(h) {} |
| 31 | 59 | ||
| 32 | u32 hex; | 60 | u32 hex; |
| 33 | 61 | ||
| 34 | BitField< 0, 16, CommandId> cmd_id; | 62 | BitField< 0, 16, Regs::Id> cmd_id; |
| 35 | BitField<16, 4, u32> parameter_mask; | 63 | BitField<16, 4, u32> parameter_mask; |
| 36 | BitField<20, 11, u32> extra_data_length; | 64 | BitField<20, 11, u32> extra_data_length; |
| 37 | BitField<31, 1, u32> group_commands; | 65 | BitField<31, 1, u32> group_commands; |
| 38 | }; | 66 | }; |
| 39 | 67 | ||
| 40 | static std::map<CommandId, const char*> command_names = { | 68 | static std::map<Regs::Id, const char*> command_names = { |
| 41 | {CommandId::ViewportSizeX, "ViewportSizeX" }, | 69 | {Regs::ViewportSizeX, "ViewportSizeX" }, |
| 42 | {CommandId::ViewportInvSizeX, "ViewportInvSizeX" }, | 70 | {Regs::ViewportInvSizeX, "ViewportInvSizeX" }, |
| 43 | {CommandId::ViewportSizeY, "ViewportSizeY" }, | 71 | {Regs::ViewportSizeY, "ViewportSizeY" }, |
| 44 | {CommandId::ViewportInvSizeY, "ViewportInvSizeY" }, | 72 | {Regs::ViewportInvSizeY, "ViewportInvSizeY" }, |
| 45 | {CommandId::ViewportCorner, "ViewportCorner" }, | 73 | {Regs::ViewportCorner, "ViewportCorner" }, |
| 46 | {CommandId::DepthBufferFormat, "DepthBufferFormat" }, | 74 | {Regs::DepthBufferFormat, "DepthBufferFormat" }, |
| 47 | {CommandId::ColorBufferFormat, "ColorBufferFormat" }, | 75 | {Regs::ColorBufferFormat, "ColorBufferFormat" }, |
| 48 | {CommandId::DepthBufferAddress, "DepthBufferAddress" }, | 76 | {Regs::DepthBufferAddress, "DepthBufferAddress" }, |
| 49 | {CommandId::ColorBufferAddress, "ColorBufferAddress" }, | 77 | {Regs::ColorBufferAddress, "ColorBufferAddress" }, |
| 50 | {CommandId::ColorBufferSize, "ColorBufferSize" }, | 78 | {Regs::ColorBufferSize, "ColorBufferSize" }, |
| 51 | }; | 79 | }; |
| 52 | 80 | ||
| 53 | } | 81 | template<> |
| 82 | union Regs::Struct<Regs::ViewportSizeX> { | ||
| 83 | BitField<0, 24, u32> value; | ||
| 84 | }; | ||
| 85 | |||
| 86 | template<> | ||
| 87 | union Regs::Struct<Regs::ViewportSizeY> { | ||
| 88 | BitField<0, 24, u32> value; | ||
| 89 | }; | ||
| 90 | |||
| 91 | template<> | ||
| 92 | union Regs::Struct<Regs::VertexDescriptor> { | ||
| 93 | enum class Format : u64 { | ||
| 94 | BYTE = 0, | ||
| 95 | UBYTE = 1, | ||
| 96 | SHORT = 2, | ||
| 97 | FLOAT = 3, | ||
| 98 | }; | ||
| 99 | |||
| 100 | BitField< 0, 2, Format> format0; | ||
| 101 | BitField< 2, 2, u64> size0; // number of elements minus 1 | ||
| 102 | BitField< 4, 2, Format> format1; | ||
| 103 | BitField< 6, 2, u64> size1; | ||
| 104 | BitField< 8, 2, Format> format2; | ||
| 105 | BitField<10, 2, u64> size2; | ||
| 106 | BitField<12, 2, Format> format3; | ||
| 107 | BitField<14, 2, u64> size3; | ||
| 108 | BitField<16, 2, Format> format4; | ||
| 109 | BitField<18, 2, u64> size4; | ||
| 110 | BitField<20, 2, Format> format5; | ||
| 111 | BitField<22, 2, u64> size5; | ||
| 112 | BitField<24, 2, Format> format6; | ||
| 113 | BitField<26, 2, u64> size6; | ||
| 114 | BitField<28, 2, Format> format7; | ||
| 115 | BitField<30, 2, u64> size7; | ||
| 116 | BitField<32, 2, Format> format8; | ||
| 117 | BitField<34, 2, u64> size8; | ||
| 118 | BitField<36, 2, Format> format9; | ||
| 119 | BitField<38, 2, u64> size9; | ||
| 120 | BitField<40, 2, Format> format10; | ||
| 121 | BitField<42, 2, u64> size10; | ||
| 122 | BitField<44, 2, Format> format11; | ||
| 123 | BitField<46, 2, u64> size11; | ||
| 124 | |||
| 125 | BitField<48, 12, u64> attribute_mask; | ||
| 126 | BitField<60, 4, u64> num_attributes; // number of total attributes minus 1 | ||
| 127 | }; | ||
| 128 | |||
| 129 | |||
| 130 | } // namespace | ||