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| author | 2014-12-04 17:37:59 +0100 | |
|---|---|---|
| committer | 2014-12-20 18:05:53 +0100 | |
| commit | 0fba1d48a6ab7a9fa19ce65ec864da212ceb501a (patch) | |
| tree | 37f0efbdb2e27c3d27828def51682329953b8683 /src/video_core | |
| parent | Pica/DebugUtils: Add support for RGBA8, RGBA5551, RGBA4 and A8 texture formats. (diff) | |
| download | yuzu-0fba1d48a6ab7a9fa19ce65ec864da212ceb501a.tar.gz yuzu-0fba1d48a6ab7a9fa19ce65ec864da212ceb501a.tar.xz yuzu-0fba1d48a6ab7a9fa19ce65ec864da212ceb501a.zip | |
Pica: Implement texture wrapping.
Diffstat (limited to 'src/video_core')
| -rw-r--r-- | src/video_core/pica.h | 12 | ||||
| -rw-r--r-- | src/video_core/rasterizer.cpp | 21 |
2 files changed, 31 insertions, 2 deletions
diff --git a/src/video_core/pica.h b/src/video_core/pica.h index 7ed49caed..ec20114fe 100644 --- a/src/video_core/pica.h +++ b/src/video_core/pica.h | |||
| @@ -104,6 +104,11 @@ struct Regs { | |||
| 104 | INSERT_PADDING_WORDS(0x17); | 104 | INSERT_PADDING_WORDS(0x17); |
| 105 | 105 | ||
| 106 | struct TextureConfig { | 106 | struct TextureConfig { |
| 107 | enum WrapMode : u32 { | ||
| 108 | ClampToEdge = 0, | ||
| 109 | Repeat = 2, | ||
| 110 | }; | ||
| 111 | |||
| 107 | INSERT_PADDING_WORDS(0x1); | 112 | INSERT_PADDING_WORDS(0x1); |
| 108 | 113 | ||
| 109 | union { | 114 | union { |
| @@ -111,7 +116,12 @@ struct Regs { | |||
| 111 | BitField<16, 16, u32> width; | 116 | BitField<16, 16, u32> width; |
| 112 | }; | 117 | }; |
| 113 | 118 | ||
| 114 | INSERT_PADDING_WORDS(0x2); | 119 | union { |
| 120 | BitField< 8, 2, WrapMode> wrap_s; | ||
| 121 | BitField<11, 2, WrapMode> wrap_t; | ||
| 122 | }; | ||
| 123 | |||
| 124 | INSERT_PADDING_WORDS(0x1); | ||
| 115 | 125 | ||
| 116 | u32 address; | 126 | u32 address; |
| 117 | 127 | ||
diff --git a/src/video_core/rasterizer.cpp b/src/video_core/rasterizer.cpp index 2ff6d19a6..e12f68a7f 100644 --- a/src/video_core/rasterizer.cpp +++ b/src/video_core/rasterizer.cpp | |||
| @@ -181,7 +181,7 @@ void ProcessTriangle(const VertexShader::OutputVertex& v0, | |||
| 181 | if (!texture.enabled) | 181 | if (!texture.enabled) |
| 182 | continue; | 182 | continue; |
| 183 | 183 | ||
| 184 | _dbg_assert_(GPU, 0 != texture.config.address); | 184 | _dbg_assert_(HW_GPU, 0 != texture.config.address); |
| 185 | 185 | ||
| 186 | // Images are split into 8x8 tiles. Each tile is composed of four 4x4 subtiles each | 186 | // Images are split into 8x8 tiles. Each tile is composed of four 4x4 subtiles each |
| 187 | // of which is composed of four 2x2 subtiles each of which is composed of four texels. | 187 | // of which is composed of four 2x2 subtiles each of which is composed of four texels. |
| @@ -206,6 +206,25 @@ void ProcessTriangle(const VertexShader::OutputVertex& v0, | |||
| 206 | // somewhat inefficient code around for now. | 206 | // somewhat inefficient code around for now. |
| 207 | int s = (int)(uv[i].u() * float24::FromFloat32(static_cast<float>(texture.config.width))).ToFloat32(); | 207 | int s = (int)(uv[i].u() * float24::FromFloat32(static_cast<float>(texture.config.width))).ToFloat32(); |
| 208 | int t = (int)(uv[i].v() * float24::FromFloat32(static_cast<float>(texture.config.height))).ToFloat32(); | 208 | int t = (int)(uv[i].v() * float24::FromFloat32(static_cast<float>(texture.config.height))).ToFloat32(); |
| 209 | auto GetWrappedTexCoord = [](Regs::TextureConfig::WrapMode mode, int val, unsigned size) { | ||
| 210 | switch (mode) { | ||
| 211 | case Regs::TextureConfig::ClampToEdge: | ||
| 212 | val = std::max(val, 0); | ||
| 213 | val = std::min(val, (int)size - 1); | ||
| 214 | return val; | ||
| 215 | |||
| 216 | case Regs::TextureConfig::Repeat: | ||
| 217 | return (int)(((unsigned)val) % size); | ||
| 218 | |||
| 219 | default: | ||
| 220 | LOG_ERROR(HW_GPU, "Unknown texture coordinate wrapping mode %x\n", (int)mode); | ||
| 221 | _dbg_assert_(HW_GPU, 0); | ||
| 222 | return 0; | ||
| 223 | } | ||
| 224 | }; | ||
| 225 | s = GetWrappedTexCoord(registers.texture0.wrap_s, s, registers.texture0.width); | ||
| 226 | t = GetWrappedTexCoord(registers.texture0.wrap_t, t, registers.texture0.height); | ||
| 227 | |||
| 209 | int texel_index_within_tile = 0; | 228 | int texel_index_within_tile = 0; |
| 210 | for (int block_size_index = 0; block_size_index < 3; ++block_size_index) { | 229 | for (int block_size_index = 0; block_size_index < 3; ++block_size_index) { |
| 211 | int sub_tile_width = 1 << block_size_index; | 230 | int sub_tile_width = 1 << block_size_index; |