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| author | 2019-11-12 10:07:22 -0400 | |
|---|---|---|
| committer | 2019-11-14 11:15:27 -0400 | |
| commit | f3d1b370aa0fd614cf28f8a609b70906d40da751 (patch) | |
| tree | 028b5f4b34c30d477e6989b49540db508a8db075 /src/video_core/shader | |
| parent | Shader_Bytecode: Add encodings for FLO, SHF and TXD (diff) | |
| download | yuzu-f3d1b370aa0fd614cf28f8a609b70906d40da751.tar.gz yuzu-f3d1b370aa0fd614cf28f8a609b70906d40da751.tar.xz yuzu-f3d1b370aa0fd614cf28f8a609b70906d40da751.zip | |
Shader_IR: Implement FLO instruction.
Diffstat (limited to 'src/video_core/shader')
| -rw-r--r-- | src/video_core/shader/decode/arithmetic_integer.cpp | 18 | ||||
| -rw-r--r-- | src/video_core/shader/node.h | 2 |
2 files changed, 20 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic_integer.cpp b/src/video_core/shader/decode/arithmetic_integer.cpp index a33d242e9..9208b7bef 100644 --- a/src/video_core/shader/decode/arithmetic_integer.cpp +++ b/src/video_core/shader/decode/arithmetic_integer.cpp | |||
| @@ -130,6 +130,24 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) { | |||
| 130 | SetRegister(bb, instr.gpr0, value); | 130 | SetRegister(bb, instr.gpr0, value); |
| 131 | break; | 131 | break; |
| 132 | } | 132 | } |
| 133 | case OpCode::Id::FLO_R: | ||
| 134 | case OpCode::Id::FLO_C: | ||
| 135 | case OpCode::Id::FLO_IMM: { | ||
| 136 | Node value; | ||
| 137 | if (instr.flo.invert) { | ||
| 138 | op_b = Operation(OperationCode::IBitwiseNot, NO_PRECISE, op_b); | ||
| 139 | } | ||
| 140 | if (instr.flo.is_signed) { | ||
| 141 | value = Operation(OperationCode::IBitMSB, NO_PRECISE, op_b); | ||
| 142 | } else { | ||
| 143 | value = Operation(OperationCode::UBitMSB, NO_PRECISE, op_b); | ||
| 144 | } | ||
| 145 | if (instr.flo.sh) { | ||
| 146 | value = Operation(OperationCode::UBitwiseXor, NO_PRECISE, value, Immediate(31)); | ||
| 147 | } | ||
| 148 | SetRegister(bb, instr.gpr0, value); | ||
| 149 | break; | ||
| 150 | } | ||
| 133 | case OpCode::Id::SEL_C: | 151 | case OpCode::Id::SEL_C: |
| 134 | case OpCode::Id::SEL_R: | 152 | case OpCode::Id::SEL_R: |
| 135 | case OpCode::Id::SEL_IMM: { | 153 | case OpCode::Id::SEL_IMM: { |
diff --git a/src/video_core/shader/node.h b/src/video_core/shader/node.h index 54217e6a4..2d11facaf 100644 --- a/src/video_core/shader/node.h +++ b/src/video_core/shader/node.h | |||
| @@ -68,6 +68,7 @@ enum class OperationCode { | |||
| 68 | IBitfieldInsert, /// (MetaArithmetic, int base, int insert, int offset, int bits) -> int | 68 | IBitfieldInsert, /// (MetaArithmetic, int base, int insert, int offset, int bits) -> int |
| 69 | IBitfieldExtract, /// (MetaArithmetic, int value, int offset, int offset) -> int | 69 | IBitfieldExtract, /// (MetaArithmetic, int value, int offset, int offset) -> int |
| 70 | IBitCount, /// (MetaArithmetic, int) -> int | 70 | IBitCount, /// (MetaArithmetic, int) -> int |
| 71 | IBitMSB, /// (MetaArithmetic, int) -> int | ||
| 71 | 72 | ||
| 72 | UAdd, /// (MetaArithmetic, uint a, uint b) -> uint | 73 | UAdd, /// (MetaArithmetic, uint a, uint b) -> uint |
| 73 | UMul, /// (MetaArithmetic, uint a, uint b) -> uint | 74 | UMul, /// (MetaArithmetic, uint a, uint b) -> uint |
| @@ -86,6 +87,7 @@ enum class OperationCode { | |||
| 86 | UBitfieldInsert, /// (MetaArithmetic, uint base, uint insert, int offset, int bits) -> uint | 87 | UBitfieldInsert, /// (MetaArithmetic, uint base, uint insert, int offset, int bits) -> uint |
| 87 | UBitfieldExtract, /// (MetaArithmetic, uint value, int offset, int offset) -> uint | 88 | UBitfieldExtract, /// (MetaArithmetic, uint value, int offset, int offset) -> uint |
| 88 | UBitCount, /// (MetaArithmetic, uint) -> uint | 89 | UBitCount, /// (MetaArithmetic, uint) -> uint |
| 90 | UBitMSB, /// (MetaArithmetic, uint) -> uint | ||
| 89 | 91 | ||
| 90 | HAdd, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2 | 92 | HAdd, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2 |
| 91 | HMul, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2 | 93 | HMul, /// (MetaArithmetic, f16vec2 a, f16vec2 b) -> f16vec2 |