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authorGravatar bunnei2015-08-15 16:51:32 -0400
committerGravatar bunnei2015-08-15 18:03:27 -0400
commitdb97090cad236eeeb0909eb1d35cbece15e1f0a5 (patch)
tree9ea9a86da4027126914e69b12c24d2849fdb2c2d /src/video_core/shader/shader.h
parentRename ARCHITECTURE_X64 definition to ARCHITECTURE_x86_64. (diff)
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Shader: Use a POD struct for registers.
Diffstat (limited to 'src/video_core/shader/shader.h')
-rw-r--r--src/video_core/shader/shader.h21
1 files changed, 12 insertions, 9 deletions
diff --git a/src/video_core/shader/shader.h b/src/video_core/shader/shader.h
index 5825e9983..2007a2844 100644
--- a/src/video_core/shader/shader.h
+++ b/src/video_core/shader/shader.h
@@ -79,11 +79,14 @@ static_assert(sizeof(OutputVertex) == 32 * sizeof(float), "OutputVertex has inva
79 * here will make it easier for us to parallelize the shader processing later. 79 * here will make it easier for us to parallelize the shader processing later.
80 */ 80 */
81struct UnitState { 81struct UnitState {
82 // The registers are accessed by the shader JIT using SSE instructions, and are therefore 82 struct Registers {
83 // required to be 16-byte aligned. 83 // The registers are accessed by the shader JIT using SSE instructions, and are therefore
84 Math::Vec4<float24> MEMORY_ALIGNED16(input_registers[16]); 84 // required to be 16-byte aligned.
85 Math::Vec4<float24> MEMORY_ALIGNED16(output_registers[16]); 85 Math::Vec4<float24> MEMORY_ALIGNED16(input[16]);
86 Math::Vec4<float24> MEMORY_ALIGNED16(temporary_registers[16]); 86 Math::Vec4<float24> MEMORY_ALIGNED16(output[16]);
87 Math::Vec4<float24> MEMORY_ALIGNED16(temporary[16]);
88 } registers;
89 static_assert(std::is_pod<Registers>::value, "Structure is not POD");
87 90
88 u32 program_counter; 91 u32 program_counter;
89 bool conditional_code[2]; 92 bool conditional_code[2];
@@ -116,10 +119,10 @@ struct UnitState {
116 static int InputOffset(const SourceRegister& reg) { 119 static int InputOffset(const SourceRegister& reg) {
117 switch (reg.GetRegisterType()) { 120 switch (reg.GetRegisterType()) {
118 case RegisterType::Input: 121 case RegisterType::Input:
119 return (int)offsetof(UnitState, input_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>); 122 return (int)offsetof(UnitState::Registers, input) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
120 123
121 case RegisterType::Temporary: 124 case RegisterType::Temporary:
122 return (int)offsetof(UnitState, temporary_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>); 125 return (int)offsetof(UnitState::Registers, temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
123 126
124 default: 127 default:
125 UNREACHABLE(); 128 UNREACHABLE();
@@ -130,10 +133,10 @@ struct UnitState {
130 static int OutputOffset(const DestRegister& reg) { 133 static int OutputOffset(const DestRegister& reg) {
131 switch (reg.GetRegisterType()) { 134 switch (reg.GetRegisterType()) {
132 case RegisterType::Output: 135 case RegisterType::Output:
133 return (int)offsetof(UnitState, output_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>); 136 return (int)offsetof(UnitState::Registers, output) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
134 137
135 case RegisterType::Temporary: 138 case RegisterType::Temporary:
136 return (int)offsetof(UnitState, temporary_registers) + reg.GetIndex()*sizeof(Math::Vec4<float24>); 139 return (int)offsetof(UnitState::Registers, temporary) + reg.GetIndex()*sizeof(Math::Vec4<float24>);
137 140
138 default: 141 default:
139 UNREACHABLE(); 142 UNREACHABLE();