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| author | 2017-01-28 13:03:13 -0800 | |
|---|---|---|
| committer | 2017-02-04 13:59:11 -0800 | |
| commit | f7c7f422c6995a31c1a16c0865bbe13bb38469a3 (patch) | |
| tree | 6dca1dfe528cc115dd1be8d6dd7a97f491140540 /src/video_core/shader/shader.cpp | |
| parent | VideoCore: Split geometry pipeline regs from Regs struct (diff) | |
| download | yuzu-f7c7f422c6995a31c1a16c0865bbe13bb38469a3.tar.gz yuzu-f7c7f422c6995a31c1a16c0865bbe13bb38469a3.tar.xz yuzu-f7c7f422c6995a31c1a16c0865bbe13bb38469a3.zip | |
VideoCore: Split shader regs from Regs struct
Diffstat (limited to 'src/video_core/shader/shader.cpp')
| -rw-r--r-- | src/video_core/shader/shader.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/video_core/shader/shader.cpp b/src/video_core/shader/shader.cpp index 916ea8823..840777a66 100644 --- a/src/video_core/shader/shader.cpp +++ b/src/video_core/shader/shader.cpp | |||
| @@ -66,7 +66,7 @@ OutputVertex OutputVertex::FromAttributeBuffer(const RasterizerRegs& regs, Attri | |||
| 66 | return ret; | 66 | return ret; |
| 67 | } | 67 | } |
| 68 | 68 | ||
| 69 | void UnitState::LoadInput(const Regs::ShaderConfig& config, const AttributeBuffer& input) { | 69 | void UnitState::LoadInput(const ShaderRegs& config, const AttributeBuffer& input) { |
| 70 | const unsigned max_attribute = config.max_input_attribute_index; | 70 | const unsigned max_attribute = config.max_input_attribute_index; |
| 71 | 71 | ||
| 72 | for (unsigned attr = 0; attr <= max_attribute; ++attr) { | 72 | for (unsigned attr = 0; attr <= max_attribute; ++attr) { |
| @@ -75,7 +75,7 @@ void UnitState::LoadInput(const Regs::ShaderConfig& config, const AttributeBuffe | |||
| 75 | } | 75 | } |
| 76 | } | 76 | } |
| 77 | 77 | ||
| 78 | void UnitState::WriteOutput(const Regs::ShaderConfig& config, AttributeBuffer& output) { | 78 | void UnitState::WriteOutput(const ShaderRegs& config, AttributeBuffer& output) { |
| 79 | unsigned int output_i = 0; | 79 | unsigned int output_i = 0; |
| 80 | for (unsigned int reg : Common::BitSet<u32>(config.output_mask)) { | 80 | for (unsigned int reg : Common::BitSet<u32>(config.output_mask)) { |
| 81 | output.attr[output_i++] = registers.output[reg]; | 81 | output.attr[output_i++] = registers.output[reg]; |