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| author | 2018-12-24 02:24:38 -0300 | |
|---|---|---|
| committer | 2019-01-15 17:54:53 -0300 | |
| commit | e1fea1e0c594cc7c5a404e7006a4b4b2f29200ae (patch) | |
| tree | 269b0a3512d9ee97bbe7ef1e0df9ec8697056939 /src/video_core/shader/decode | |
| parent | shader_decode: Implement VMAD and VSETP (diff) | |
| download | yuzu-e1fea1e0c594cc7c5a404e7006a4b4b2f29200ae.tar.gz yuzu-e1fea1e0c594cc7c5a404e7006a4b4b2f29200ae.tar.xz yuzu-e1fea1e0c594cc7c5a404e7006a4b4b2f29200ae.zip | |
video_core: Implement IR based geometry shaders
Diffstat (limited to 'src/video_core/shader/decode')
| -rw-r--r-- | src/video_core/shader/decode/other.cpp | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index 9630ef831..1918762b8 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp | |||
| @@ -12,6 +12,7 @@ namespace VideoCommon::Shader { | |||
| 12 | using Tegra::Shader::ConditionCode; | 12 | using Tegra::Shader::ConditionCode; |
| 13 | using Tegra::Shader::Instruction; | 13 | using Tegra::Shader::Instruction; |
| 14 | using Tegra::Shader::OpCode; | 14 | using Tegra::Shader::OpCode; |
| 15 | using Tegra::Shader::Register; | ||
| 15 | 16 | ||
| 16 | u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { | 17 | u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { |
| 17 | const Instruction instr = {program_code[pc]}; | 18 | const Instruction instr = {program_code[pc]}; |
| @@ -140,6 +141,30 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) { | |||
| 140 | SetRegister(bb, instr.gpr0, value); | 141 | SetRegister(bb, instr.gpr0, value); |
| 141 | break; | 142 | break; |
| 142 | } | 143 | } |
| 144 | case OpCode::Id::OUT_R: { | ||
| 145 | UNIMPLEMENTED_IF_MSG(instr.gpr20.Value() != Register::ZeroIndex, | ||
| 146 | "Stream buffer is not supported"); | ||
| 147 | |||
| 148 | if (instr.out.emit) { | ||
| 149 | // gpr0 is used to store the next address and gpr8 contains the address to emit. | ||
| 150 | // Hardware uses pointers here but we just ignore it | ||
| 151 | bb.push_back(Operation(OperationCode::EmitVertex)); | ||
| 152 | SetRegister(bb, instr.gpr0, Immediate(0)); | ||
| 153 | } | ||
| 154 | if (instr.out.cut) { | ||
| 155 | bb.push_back(Operation(OperationCode::EndPrimitive)); | ||
| 156 | } | ||
| 157 | break; | ||
| 158 | } | ||
| 159 | case OpCode::Id::ISBERD: { | ||
| 160 | UNIMPLEMENTED_IF(instr.isberd.o != 0); | ||
| 161 | UNIMPLEMENTED_IF(instr.isberd.skew != 0); | ||
| 162 | UNIMPLEMENTED_IF(instr.isberd.shift != Tegra::Shader::IsberdShift::None); | ||
| 163 | UNIMPLEMENTED_IF(instr.isberd.mode != Tegra::Shader::IsberdMode::None); | ||
| 164 | LOG_WARNING(HW_GPU, "ISBERD instruction is incomplete"); | ||
| 165 | SetRegister(bb, instr.gpr0, GetRegister(instr.gpr8)); | ||
| 166 | break; | ||
| 167 | } | ||
| 143 | case OpCode::Id::DEPBAR: { | 168 | case OpCode::Id::DEPBAR: { |
| 144 | LOG_WARNING(HW_GPU, "DEPBAR instruction is stubbed"); | 169 | LOG_WARNING(HW_GPU, "DEPBAR instruction is stubbed"); |
| 145 | break; | 170 | break; |