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| author | 2019-05-03 03:00:51 -0300 | |
|---|---|---|
| committer | 2019-05-20 16:36:49 -0300 | |
| commit | 9c3461604cff25ef11ecb6937f904eac37090ee7 (patch) | |
| tree | f6ce8922bfd63ec15c1f71e12c592f26cf94c79c /src/video_core/shader/decode | |
| parent | gl_shader_decompiler: Make GetSwizzle constexpr (diff) | |
| download | yuzu-9c3461604cff25ef11ecb6937f904eac37090ee7.tar.gz yuzu-9c3461604cff25ef11ecb6937f904eac37090ee7.tar.xz yuzu-9c3461604cff25ef11ecb6937f904eac37090ee7.zip | |
shader: Implement S2R Tid{XYZ} and CtaId{XYZ}
Diffstat (limited to 'src/video_core/shader/decode')
| -rw-r--r-- | src/video_core/shader/decode/other.cpp | 42 |
1 files changed, 28 insertions, 14 deletions
diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp index fa17c45b5..77c6f9951 100644 --- a/src/video_core/shader/decode/other.cpp +++ b/src/video_core/shader/decode/other.cpp | |||
| @@ -13,6 +13,7 @@ using Tegra::Shader::ConditionCode; | |||
| 13 | using Tegra::Shader::Instruction; | 13 | using Tegra::Shader::Instruction; |
| 14 | using Tegra::Shader::OpCode; | 14 | using Tegra::Shader::OpCode; |
| 15 | using Tegra::Shader::Register; | 15 | using Tegra::Shader::Register; |
| 16 | using Tegra::Shader::SystemVariable; | ||
| 16 | 17 | ||
| 17 | u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) { | 18 | u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) { |
| 18 | const Instruction instr = {program_code[pc]}; | 19 | const Instruction instr = {program_code[pc]}; |
| @@ -58,20 +59,33 @@ u32 ShaderIR::DecodeOther(NodeBlock& bb, u32 pc) { | |||
| 58 | break; | 59 | break; |
| 59 | } | 60 | } |
| 60 | case OpCode::Id::MOV_SYS: { | 61 | case OpCode::Id::MOV_SYS: { |
| 61 | switch (instr.sys20) { | 62 | const Node value = [&]() { |
| 62 | case Tegra::Shader::SystemVariable::InvocationInfo: { | 63 | switch (instr.sys20) { |
| 63 | LOG_WARNING(HW_GPU, "MOV_SYS instruction with InvocationInfo is incomplete"); | 64 | case SystemVariable::Ydirection: |
| 64 | SetRegister(bb, instr.gpr0, Immediate(0u)); | 65 | return Operation(OperationCode::YNegate); |
| 65 | break; | 66 | case SystemVariable::InvocationInfo: |
| 66 | } | 67 | LOG_WARNING(HW_GPU, "MOV_SYS instruction with InvocationInfo is incomplete"); |
| 67 | case Tegra::Shader::SystemVariable::Ydirection: { | 68 | return Immediate(0u); |
| 68 | // Config pack's third value is Y_NEGATE's state. | 69 | case SystemVariable::TidX: |
| 69 | SetRegister(bb, instr.gpr0, Operation(OperationCode::YNegate)); | 70 | return Operation(OperationCode::LocalInvocationIdX); |
| 70 | break; | 71 | case SystemVariable::TidY: |
| 71 | } | 72 | return Operation(OperationCode::LocalInvocationIdY); |
| 72 | default: | 73 | case SystemVariable::TidZ: |
| 73 | UNIMPLEMENTED_MSG("Unhandled system move: {}", static_cast<u32>(instr.sys20.Value())); | 74 | return Operation(OperationCode::LocalInvocationIdZ); |
| 74 | } | 75 | case SystemVariable::CtaIdX: |
| 76 | return Operation(OperationCode::WorkGroupIdX); | ||
| 77 | case SystemVariable::CtaIdY: | ||
| 78 | return Operation(OperationCode::WorkGroupIdY); | ||
| 79 | case SystemVariable::CtaIdZ: | ||
| 80 | return Operation(OperationCode::WorkGroupIdZ); | ||
| 81 | default: | ||
| 82 | UNIMPLEMENTED_MSG("Unhandled system move: {}", | ||
| 83 | static_cast<u32>(instr.sys20.Value())); | ||
| 84 | return Immediate(0u); | ||
| 85 | } | ||
| 86 | }(); | ||
| 87 | SetRegister(bb, instr.gpr0, value); | ||
| 88 | |||
| 75 | break; | 89 | break; |
| 76 | } | 90 | } |
| 77 | case OpCode::Id::BRA: { | 91 | case OpCode::Id::BRA: { |