diff options
| author | 2019-02-06 21:56:14 -0500 | |
|---|---|---|
| committer | 2019-02-06 21:56:14 -0500 | |
| commit | f09d1dffd16ab857d6cf75b862aa0b01777e5673 (patch) | |
| tree | 8d99905781788745e7a058cdb844964bbc15eba4 /src/video_core/shader/decode.cpp | |
| parent | Merge pull request #2091 from FearlessTobi/port-4603 (diff) | |
| parent | shader/track: Search inside of conditional nodes (diff) | |
| download | yuzu-f09d1dffd16ab857d6cf75b862aa0b01777e5673.tar.gz yuzu-f09d1dffd16ab857d6cf75b862aa0b01777e5673.tar.xz yuzu-f09d1dffd16ab857d6cf75b862aa0b01777e5673.zip | |
Merge pull request #2083 from ReinUsesLisp/shader-ir-cbuf-tracking
shader/track: Add a more permissive global memory tracking
Diffstat (limited to 'src/video_core/shader/decode.cpp')
| -rw-r--r-- | src/video_core/shader/decode.cpp | 72 |
1 files changed, 37 insertions, 35 deletions
diff --git a/src/video_core/shader/decode.cpp b/src/video_core/shader/decode.cpp index 812983a99..740ac3118 100644 --- a/src/video_core/shader/decode.cpp +++ b/src/video_core/shader/decode.cpp | |||
| @@ -121,15 +121,15 @@ ExitMethod ShaderIR::Scan(u32 begin, u32 end, std::set<u32>& labels) { | |||
| 121 | return exit_method = ExitMethod::AlwaysReturn; | 121 | return exit_method = ExitMethod::AlwaysReturn; |
| 122 | } | 122 | } |
| 123 | 123 | ||
| 124 | BasicBlock ShaderIR::DecodeRange(u32 begin, u32 end) { | 124 | NodeBlock ShaderIR::DecodeRange(u32 begin, u32 end) { |
| 125 | BasicBlock basic_block; | 125 | NodeBlock basic_block; |
| 126 | for (u32 pc = begin; pc < (begin > end ? MAX_PROGRAM_LENGTH : end);) { | 126 | for (u32 pc = begin; pc < (begin > end ? MAX_PROGRAM_LENGTH : end);) { |
| 127 | pc = DecodeInstr(basic_block, pc); | 127 | pc = DecodeInstr(basic_block, pc); |
| 128 | } | 128 | } |
| 129 | return basic_block; | 129 | return basic_block; |
| 130 | } | 130 | } |
| 131 | 131 | ||
| 132 | u32 ShaderIR::DecodeInstr(BasicBlock& bb, u32 pc) { | 132 | u32 ShaderIR::DecodeInstr(NodeBlock& bb, u32 pc) { |
| 133 | // Ignore sched instructions when generating code. | 133 | // Ignore sched instructions when generating code. |
| 134 | if (IsSchedInstruction(pc, main_offset)) { | 134 | if (IsSchedInstruction(pc, main_offset)) { |
| 135 | return pc + 1; | 135 | return pc + 1; |
| @@ -151,39 +151,38 @@ u32 ShaderIR::DecodeInstr(BasicBlock& bb, u32 pc) { | |||
| 151 | UNIMPLEMENTED_IF_MSG(instr.pred.full_pred == Pred::NeverExecute, | 151 | UNIMPLEMENTED_IF_MSG(instr.pred.full_pred == Pred::NeverExecute, |
| 152 | "NeverExecute predicate not implemented"); | 152 | "NeverExecute predicate not implemented"); |
| 153 | 153 | ||
| 154 | static const std::map<OpCode::Type, u32 (ShaderIR::*)(BasicBlock&, const BasicBlock&, u32)> | 154 | static const std::map<OpCode::Type, u32 (ShaderIR::*)(NodeBlock&, u32)> decoders = { |
| 155 | decoders = { | 155 | {OpCode::Type::Arithmetic, &ShaderIR::DecodeArithmetic}, |
| 156 | {OpCode::Type::Arithmetic, &ShaderIR::DecodeArithmetic}, | 156 | {OpCode::Type::ArithmeticImmediate, &ShaderIR::DecodeArithmeticImmediate}, |
| 157 | {OpCode::Type::ArithmeticImmediate, &ShaderIR::DecodeArithmeticImmediate}, | 157 | {OpCode::Type::Bfe, &ShaderIR::DecodeBfe}, |
| 158 | {OpCode::Type::Bfe, &ShaderIR::DecodeBfe}, | 158 | {OpCode::Type::Bfi, &ShaderIR::DecodeBfi}, |
| 159 | {OpCode::Type::Bfi, &ShaderIR::DecodeBfi}, | 159 | {OpCode::Type::Shift, &ShaderIR::DecodeShift}, |
| 160 | {OpCode::Type::Shift, &ShaderIR::DecodeShift}, | 160 | {OpCode::Type::ArithmeticInteger, &ShaderIR::DecodeArithmeticInteger}, |
| 161 | {OpCode::Type::ArithmeticInteger, &ShaderIR::DecodeArithmeticInteger}, | 161 | {OpCode::Type::ArithmeticIntegerImmediate, &ShaderIR::DecodeArithmeticIntegerImmediate}, |
| 162 | {OpCode::Type::ArithmeticIntegerImmediate, &ShaderIR::DecodeArithmeticIntegerImmediate}, | 162 | {OpCode::Type::ArithmeticHalf, &ShaderIR::DecodeArithmeticHalf}, |
| 163 | {OpCode::Type::ArithmeticHalf, &ShaderIR::DecodeArithmeticHalf}, | 163 | {OpCode::Type::ArithmeticHalfImmediate, &ShaderIR::DecodeArithmeticHalfImmediate}, |
| 164 | {OpCode::Type::ArithmeticHalfImmediate, &ShaderIR::DecodeArithmeticHalfImmediate}, | 164 | {OpCode::Type::Ffma, &ShaderIR::DecodeFfma}, |
| 165 | {OpCode::Type::Ffma, &ShaderIR::DecodeFfma}, | 165 | {OpCode::Type::Hfma2, &ShaderIR::DecodeHfma2}, |
| 166 | {OpCode::Type::Hfma2, &ShaderIR::DecodeHfma2}, | 166 | {OpCode::Type::Conversion, &ShaderIR::DecodeConversion}, |
| 167 | {OpCode::Type::Conversion, &ShaderIR::DecodeConversion}, | 167 | {OpCode::Type::Memory, &ShaderIR::DecodeMemory}, |
| 168 | {OpCode::Type::Memory, &ShaderIR::DecodeMemory}, | 168 | {OpCode::Type::FloatSetPredicate, &ShaderIR::DecodeFloatSetPredicate}, |
| 169 | {OpCode::Type::FloatSetPredicate, &ShaderIR::DecodeFloatSetPredicate}, | 169 | {OpCode::Type::IntegerSetPredicate, &ShaderIR::DecodeIntegerSetPredicate}, |
| 170 | {OpCode::Type::IntegerSetPredicate, &ShaderIR::DecodeIntegerSetPredicate}, | 170 | {OpCode::Type::HalfSetPredicate, &ShaderIR::DecodeHalfSetPredicate}, |
| 171 | {OpCode::Type::HalfSetPredicate, &ShaderIR::DecodeHalfSetPredicate}, | 171 | {OpCode::Type::PredicateSetRegister, &ShaderIR::DecodePredicateSetRegister}, |
| 172 | {OpCode::Type::PredicateSetRegister, &ShaderIR::DecodePredicateSetRegister}, | 172 | {OpCode::Type::PredicateSetPredicate, &ShaderIR::DecodePredicateSetPredicate}, |
| 173 | {OpCode::Type::PredicateSetPredicate, &ShaderIR::DecodePredicateSetPredicate}, | 173 | {OpCode::Type::RegisterSetPredicate, &ShaderIR::DecodeRegisterSetPredicate}, |
| 174 | {OpCode::Type::RegisterSetPredicate, &ShaderIR::DecodeRegisterSetPredicate}, | 174 | {OpCode::Type::FloatSet, &ShaderIR::DecodeFloatSet}, |
| 175 | {OpCode::Type::FloatSet, &ShaderIR::DecodeFloatSet}, | 175 | {OpCode::Type::IntegerSet, &ShaderIR::DecodeIntegerSet}, |
| 176 | {OpCode::Type::IntegerSet, &ShaderIR::DecodeIntegerSet}, | 176 | {OpCode::Type::HalfSet, &ShaderIR::DecodeHalfSet}, |
| 177 | {OpCode::Type::HalfSet, &ShaderIR::DecodeHalfSet}, | 177 | {OpCode::Type::Video, &ShaderIR::DecodeVideo}, |
| 178 | {OpCode::Type::Video, &ShaderIR::DecodeVideo}, | 178 | {OpCode::Type::Xmad, &ShaderIR::DecodeXmad}, |
| 179 | {OpCode::Type::Xmad, &ShaderIR::DecodeXmad}, | 179 | }; |
| 180 | }; | ||
| 181 | 180 | ||
| 182 | std::vector<Node> tmp_block; | 181 | std::vector<Node> tmp_block; |
| 183 | if (const auto decoder = decoders.find(opcode->get().GetType()); decoder != decoders.end()) { | 182 | if (const auto decoder = decoders.find(opcode->get().GetType()); decoder != decoders.end()) { |
| 184 | pc = (this->*decoder->second)(tmp_block, bb, pc); | 183 | pc = (this->*decoder->second)(tmp_block, pc); |
| 185 | } else { | 184 | } else { |
| 186 | pc = DecodeOther(tmp_block, bb, pc); | 185 | pc = DecodeOther(tmp_block, pc); |
| 187 | } | 186 | } |
| 188 | 187 | ||
| 189 | // Some instructions (like SSY) don't have a predicate field, they are always unconditionally | 188 | // Some instructions (like SSY) don't have a predicate field, they are always unconditionally |
| @@ -192,11 +191,14 @@ u32 ShaderIR::DecodeInstr(BasicBlock& bb, u32 pc) { | |||
| 192 | const auto pred_index = static_cast<u32>(instr.pred.pred_index); | 191 | const auto pred_index = static_cast<u32>(instr.pred.pred_index); |
| 193 | 192 | ||
| 194 | if (can_be_predicated && pred_index != static_cast<u32>(Pred::UnusedIndex)) { | 193 | if (can_be_predicated && pred_index != static_cast<u32>(Pred::UnusedIndex)) { |
| 195 | bb.push_back( | 194 | const Node conditional = |
| 196 | Conditional(GetPredicate(pred_index, instr.negate_pred != 0), std::move(tmp_block))); | 195 | Conditional(GetPredicate(pred_index, instr.negate_pred != 0), std::move(tmp_block)); |
| 196 | global_code.push_back(conditional); | ||
| 197 | bb.push_back(conditional); | ||
| 197 | } else { | 198 | } else { |
| 198 | for (auto& node : tmp_block) { | 199 | for (auto& node : tmp_block) { |
| 199 | bb.push_back(std::move(node)); | 200 | global_code.push_back(node); |
| 201 | bb.push_back(node); | ||
| 200 | } | 202 | } |
| 201 | } | 203 | } |
| 202 | 204 | ||