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| author | 2019-09-24 23:34:18 -0300 | |
|---|---|---|
| committer | 2019-10-25 09:01:31 -0400 | |
| commit | 7b81ba4d8a9805f808fcc60a0905ac74d293b2ee (patch) | |
| tree | 7bf80df3851e7d0e25746d241cbb0e09ba5c6b33 /src/video_core/shader/decode.cpp | |
| parent | Shader_IR: Implement Fast BRX and allow multi-branches in the CFG. (diff) | |
| download | yuzu-7b81ba4d8a9805f808fcc60a0905ac74d293b2ee.tar.gz yuzu-7b81ba4d8a9805f808fcc60a0905ac74d293b2ee.tar.xz yuzu-7b81ba4d8a9805f808fcc60a0905ac74d293b2ee.zip | |
gl_shader_decompiler: Move entries to a separate function
Diffstat (limited to 'src/video_core/shader/decode.cpp')
| -rw-r--r-- | src/video_core/shader/decode.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/video_core/shader/decode.cpp b/src/video_core/shader/decode.cpp index 053241128..e1afa4582 100644 --- a/src/video_core/shader/decode.cpp +++ b/src/video_core/shader/decode.cpp | |||
| @@ -33,7 +33,7 @@ constexpr bool IsSchedInstruction(u32 offset, u32 main_offset) { | |||
| 33 | return (absolute_offset % SchedPeriod) == 0; | 33 | return (absolute_offset % SchedPeriod) == 0; |
| 34 | } | 34 | } |
| 35 | 35 | ||
| 36 | } // namespace | 36 | } // Anonymous namespace |
| 37 | 37 | ||
| 38 | class ASTDecoder { | 38 | class ASTDecoder { |
| 39 | public: | 39 | public: |
| @@ -102,7 +102,7 @@ void ShaderIR::Decode() { | |||
| 102 | std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header)); | 102 | std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header)); |
| 103 | 103 | ||
| 104 | decompiled = false; | 104 | decompiled = false; |
| 105 | auto info = ScanFlow(program_code, program_size, main_offset, settings, locker); | 105 | auto info = ScanFlow(program_code, main_offset, settings, locker); |
| 106 | auto& shader_info = *info; | 106 | auto& shader_info = *info; |
| 107 | coverage_begin = shader_info.start; | 107 | coverage_begin = shader_info.start; |
| 108 | coverage_end = shader_info.end; | 108 | coverage_end = shader_info.end; |
| @@ -155,7 +155,7 @@ void ShaderIR::Decode() { | |||
| 155 | [[fallthrough]]; | 155 | [[fallthrough]]; |
| 156 | case CompileDepth::BruteForce: { | 156 | case CompileDepth::BruteForce: { |
| 157 | coverage_begin = main_offset; | 157 | coverage_begin = main_offset; |
| 158 | const u32 shader_end = static_cast<u32>(program_size / sizeof(u64)); | 158 | const u32 shader_end = program_code.size(); |
| 159 | coverage_end = shader_end; | 159 | coverage_end = shader_end; |
| 160 | for (u32 label = main_offset; label < shader_end; label++) { | 160 | for (u32 label = main_offset; label < shader_end; label++) { |
| 161 | basic_blocks.insert({label, DecodeRange(label, label + 1)}); | 161 | basic_blocks.insert({label, DecodeRange(label, label + 1)}); |
| @@ -225,7 +225,8 @@ void ShaderIR::InsertControlFlow(NodeBlock& bb, const ShaderBlock& block) { | |||
| 225 | for (auto& branch_case : multi_branch->branches) { | 225 | for (auto& branch_case : multi_branch->branches) { |
| 226 | Node n = Operation(OperationCode::Branch, Immediate(branch_case.address)); | 226 | Node n = Operation(OperationCode::Branch, Immediate(branch_case.address)); |
| 227 | Node op_b = Immediate(branch_case.cmp_value); | 227 | Node op_b = Immediate(branch_case.cmp_value); |
| 228 | Node condition = GetPredicateComparisonInteger(Tegra::Shader::PredCondition::Equal, false, op_a, op_b); | 228 | Node condition = |
| 229 | GetPredicateComparisonInteger(Tegra::Shader::PredCondition::Equal, false, op_a, op_b); | ||
| 229 | auto result = Conditional(condition, {n}); | 230 | auto result = Conditional(condition, {n}); |
| 230 | bb.push_back(result); | 231 | bb.push_back(result); |
| 231 | global_code.push_back(result); | 232 | global_code.push_back(result); |