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authorGravatar Morph2022-10-13 15:52:56 -0400
committerGravatar Morph2022-10-13 15:52:56 -0400
commitd3114c620d169b05ee16a72826cfc55e9c10a56a (patch)
treea6b86c0de4e402413435984ffa2f45ee0170b1ae /src/video_core/renderer_vulkan
parentMerge pull request #9066 from Morph1984/fix-stretch-to-window (diff)
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renderer_(opengl/vulkan): Fix tessellation clockwise parameter
This should be assigned CW only on Triangles_CW rather than not Triangles_CCW, making CCW the default winding order rather than CW.
Diffstat (limited to 'src/video_core/renderer_vulkan')
-rw-r--r--src/video_core/renderer_vulkan/fixed_pipeline_state.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp b/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp
index eab1b8f93..f85ed8e5b 100644
--- a/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp
+++ b/src/video_core/renderer_vulkan/fixed_pipeline_state.cpp
@@ -73,8 +73,8 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
73 patch_control_points_minus_one.Assign(regs.patch_vertices - 1); 73 patch_control_points_minus_one.Assign(regs.patch_vertices - 1);
74 tessellation_primitive.Assign(static_cast<u32>(regs.tessellation.params.domain_type.Value())); 74 tessellation_primitive.Assign(static_cast<u32>(regs.tessellation.params.domain_type.Value()));
75 tessellation_spacing.Assign(static_cast<u32>(regs.tessellation.params.spacing.Value())); 75 tessellation_spacing.Assign(static_cast<u32>(regs.tessellation.params.spacing.Value()));
76 tessellation_clockwise.Assign(regs.tessellation.params.output_primitives.Value() != 76 tessellation_clockwise.Assign(regs.tessellation.params.output_primitives.Value() ==
77 Maxwell::Tessellation::OutputPrimitves::Triangles_CCW); 77 Maxwell::Tessellation::OutputPrimitives::Triangles_CW);
78 logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0); 78 logic_op_enable.Assign(regs.logic_op.enable != 0 ? 1 : 0);
79 logic_op.Assign(PackLogicOp(regs.logic_op.op)); 79 logic_op.Assign(PackLogicOp(regs.logic_op.op));
80 topology.Assign(regs.draw.topology); 80 topology.Assign(regs.draw.topology);