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| author | 2018-08-30 10:31:26 -0400 | |
|---|---|---|
| committer | 2018-08-30 10:31:26 -0400 | |
| commit | d6accf96ff08450f17c9ec71425037aa2dbddd7f (patch) | |
| tree | e9110ef0cd78b866ced55aac4aeeefa458c66bc9 /src/video_core/renderer_opengl | |
| parent | Merge pull request #1198 from lioncash/kernel (diff) | |
| parent | gl_shader_decompiler: Improve IPA for Pass mode with Position attribute. (diff) | |
| download | yuzu-d6accf96ff08450f17c9ec71425037aa2dbddd7f.tar.gz yuzu-d6accf96ff08450f17c9ec71425037aa2dbddd7f.tar.xz yuzu-d6accf96ff08450f17c9ec71425037aa2dbddd7f.zip | |
Merge pull request #1200 from bunnei/improve-ipa
gl_shader_decompiler: Improve IPA for Pass mode with Position attribute.
Diffstat (limited to 'src/video_core/renderer_opengl')
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 7e5ebfe24..7b6eb25a4 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -2100,7 +2100,39 @@ private: | |||
| 2100 | } | 2100 | } |
| 2101 | case OpCode::Id::IPA: { | 2101 | case OpCode::Id::IPA: { |
| 2102 | const auto& attribute = instr.attribute.fmt28; | 2102 | const auto& attribute = instr.attribute.fmt28; |
| 2103 | regs.SetRegisterToInputAttibute(instr.gpr0, attribute.element, attribute.index); | 2103 | const auto& reg = instr.gpr0; |
| 2104 | switch (instr.ipa.mode) { | ||
| 2105 | case Tegra::Shader::IpaMode::Pass: | ||
| 2106 | if (stage == Maxwell3D::Regs::ShaderStage::Fragment && | ||
| 2107 | attribute.index == Attribute::Index::Position) { | ||
| 2108 | switch (attribute.element) { | ||
| 2109 | case 0: | ||
| 2110 | shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.x;"); | ||
| 2111 | break; | ||
| 2112 | case 1: | ||
| 2113 | shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.y;"); | ||
| 2114 | break; | ||
| 2115 | case 2: | ||
| 2116 | shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.z;"); | ||
| 2117 | break; | ||
| 2118 | case 3: | ||
| 2119 | shader.AddLine(regs.GetRegisterAsFloat(reg) + " = 1.0;"); | ||
| 2120 | break; | ||
| 2121 | } | ||
| 2122 | } else { | ||
| 2123 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); | ||
| 2124 | } | ||
| 2125 | break; | ||
| 2126 | case Tegra::Shader::IpaMode::None: | ||
| 2127 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); | ||
| 2128 | break; | ||
| 2129 | default: | ||
| 2130 | LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}", | ||
| 2131 | static_cast<u32>(instr.ipa.mode.Value())); | ||
| 2132 | UNREACHABLE(); | ||
| 2133 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); | ||
| 2134 | } | ||
| 2135 | |||
| 2104 | break; | 2136 | break; |
| 2105 | } | 2137 | } |
| 2106 | case OpCode::Id::SSY: { | 2138 | case OpCode::Id::SSY: { |