diff options
| author | 2018-08-29 00:37:29 -0400 | |
|---|---|---|
| committer | 2018-08-29 00:37:29 -0400 | |
| commit | b1ccd8843467e43838e19c50dcfcbc2ff0b3bc0b (patch) | |
| tree | 12fe797d8597eab090085a46d34eb51acb9f1bc1 /src/video_core/renderer_opengl | |
| parent | Merge pull request #1193 from lioncash/priv (diff) | |
| download | yuzu-b1ccd8843467e43838e19c50dcfcbc2ff0b3bc0b.tar.gz yuzu-b1ccd8843467e43838e19c50dcfcbc2ff0b3bc0b.tar.xz yuzu-b1ccd8843467e43838e19c50dcfcbc2ff0b3bc0b.zip | |
gl_shader_decompiler: Improve IPA for Pass mode with Position attribute.
Diffstat (limited to 'src/video_core/renderer_opengl')
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 94e318966..c9fe37f74 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -2039,7 +2039,39 @@ private: | |||
| 2039 | } | 2039 | } |
| 2040 | case OpCode::Id::IPA: { | 2040 | case OpCode::Id::IPA: { |
| 2041 | const auto& attribute = instr.attribute.fmt28; | 2041 | const auto& attribute = instr.attribute.fmt28; |
| 2042 | regs.SetRegisterToInputAttibute(instr.gpr0, attribute.element, attribute.index); | 2042 | const auto& reg = instr.gpr0; |
| 2043 | switch (instr.ipa.mode) { | ||
| 2044 | case Tegra::Shader::IpaMode::Pass: | ||
| 2045 | if (stage == Maxwell3D::Regs::ShaderStage::Fragment && | ||
| 2046 | attribute.index == Attribute::Index::Position) { | ||
| 2047 | switch (attribute.element) { | ||
| 2048 | case 0: | ||
| 2049 | shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.x;"); | ||
| 2050 | break; | ||
| 2051 | case 1: | ||
| 2052 | shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.y;"); | ||
| 2053 | break; | ||
| 2054 | case 2: | ||
| 2055 | shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.z;"); | ||
| 2056 | break; | ||
| 2057 | case 3: | ||
| 2058 | shader.AddLine(regs.GetRegisterAsFloat(reg) + " = 1.0;"); | ||
| 2059 | break; | ||
| 2060 | } | ||
| 2061 | } else { | ||
| 2062 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); | ||
| 2063 | } | ||
| 2064 | break; | ||
| 2065 | case Tegra::Shader::IpaMode::None: | ||
| 2066 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); | ||
| 2067 | break; | ||
| 2068 | default: | ||
| 2069 | LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}", | ||
| 2070 | static_cast<u32>(instr.ipa.mode.Value())); | ||
| 2071 | UNREACHABLE(); | ||
| 2072 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); | ||
| 2073 | } | ||
| 2074 | |||
| 2043 | break; | 2075 | break; |
| 2044 | } | 2076 | } |
| 2045 | case OpCode::Id::SSY: { | 2077 | case OpCode::Id::SSY: { |