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| author | 2018-09-01 16:34:27 +1000 | |
|---|---|---|
| committer | 2018-09-01 16:34:27 +1000 | |
| commit | ad3dca7e62373fe9d7df50414178fe65322e6a06 (patch) | |
| tree | 640c076e8a3d49960f07d8ce6a53449e0a9523df /src/video_core/renderer_opengl | |
| parent | Merge pull request #1196 from FearlessTobi/ccache-consistency (diff) | |
| download | yuzu-ad3dca7e62373fe9d7df50414178fe65322e6a06.tar.gz yuzu-ad3dca7e62373fe9d7df50414178fe65322e6a06.tar.xz yuzu-ad3dca7e62373fe9d7df50414178fe65322e6a06.zip | |
Added better asserts to IPA, Renamed IPA modes to match mesa
IpaMode is changed to IpaInterpMode
IpaMode is suppose to be 2 bits not 3
Added IpaSampleMode
Added Saturate
Renamed modes based on
https://github.com/mesa3d/mesa/blob/d27c7918916cdc8092959124955f887592e37d72/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp#L2530
Diffstat (limited to 'src/video_core/renderer_opengl')
| -rw-r--r-- | src/video_core/renderer_opengl/gl_shader_decompiler.cpp | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 391c92d47..e3a82b0c9 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp | |||
| @@ -2110,8 +2110,12 @@ private: | |||
| 2110 | case OpCode::Id::IPA: { | 2110 | case OpCode::Id::IPA: { |
| 2111 | const auto& attribute = instr.attribute.fmt28; | 2111 | const auto& attribute = instr.attribute.fmt28; |
| 2112 | const auto& reg = instr.gpr0; | 2112 | const auto& reg = instr.gpr0; |
| 2113 | switch (instr.ipa.mode) { | 2113 | ASSERT_MSG(instr.ipa.sample_mode == Tegra::Shader::IpaSampleMode::Default, |
| 2114 | case Tegra::Shader::IpaMode::Pass: | 2114 | "Unhandled IPA sample mode: {}", |
| 2115 | static_cast<u32>(instr.ipa.sample_mode.Value())); | ||
| 2116 | ASSERT_MSG(instr.ipa.saturate == 0, "IPA saturate not implemented"); | ||
| 2117 | switch (instr.ipa.interp_mode) { | ||
| 2118 | case Tegra::Shader::IpaInterpMode::Linear: | ||
| 2115 | if (stage == Maxwell3D::Regs::ShaderStage::Fragment && | 2119 | if (stage == Maxwell3D::Regs::ShaderStage::Fragment && |
| 2116 | attribute.index == Attribute::Index::Position) { | 2120 | attribute.index == Attribute::Index::Position) { |
| 2117 | switch (attribute.element) { | 2121 | switch (attribute.element) { |
| @@ -2132,12 +2136,12 @@ private: | |||
| 2132 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); | 2136 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); |
| 2133 | } | 2137 | } |
| 2134 | break; | 2138 | break; |
| 2135 | case Tegra::Shader::IpaMode::None: | 2139 | case Tegra::Shader::IpaInterpMode::Perspective: |
| 2136 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); | 2140 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); |
| 2137 | break; | 2141 | break; |
| 2138 | default: | 2142 | default: |
| 2139 | LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}", | 2143 | LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}", |
| 2140 | static_cast<u32>(instr.ipa.mode.Value())); | 2144 | static_cast<u32>(instr.ipa.interp_mode.Value())); |
| 2141 | UNREACHABLE(); | 2145 | UNREACHABLE(); |
| 2142 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); | 2146 | regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index); |
| 2143 | } | 2147 | } |