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| author | 2020-03-22 22:25:44 +0700 | |
|---|---|---|
| committer | 2020-03-22 22:25:44 +0700 | |
| commit | fc37672f26a6f5fb7e09874b0463682c0acf3ca5 (patch) | |
| tree | f13f4bc7a75c6ef8ba9c68e2c61f6b42cac98996 /src/video_core/engines | |
| parent | maxwell_3d: change declaration order (diff) | |
| download | yuzu-fc37672f26a6f5fb7e09874b0463682c0acf3ca5.tar.gz yuzu-fc37672f26a6f5fb7e09874b0463682c0acf3ca5.tar.xz yuzu-fc37672f26a6f5fb7e09874b0463682c0acf3ca5.zip | |
apply replay logic to all writes. remove replay from MacroInterpreter::Send (@fincs)
Diffstat (limited to 'src/video_core/engines')
| -rw-r--r-- | src/video_core/engines/maxwell_3d.cpp | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index 4e4373ad9..ba63b44b4 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp | |||
| @@ -162,14 +162,17 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) { | |||
| 162 | ASSERT_MSG(method < Regs::NUM_REGS, | 162 | ASSERT_MSG(method < Regs::NUM_REGS, |
| 163 | "Invalid Maxwell3D register, increase the size of the Regs structure"); | 163 | "Invalid Maxwell3D register, increase the size of the Regs structure"); |
| 164 | 164 | ||
| 165 | u32 arg = method_call.argument; | ||
| 165 | // Keep track of the register value in shadow_state when requested. | 166 | // Keep track of the register value in shadow_state when requested. |
| 166 | if (shadow_state.shadow_ram_control == Regs::ShadowRamControl::Track || | 167 | if (shadow_state.shadow_ram_control == Regs::ShadowRamControl::Track || |
| 167 | shadow_state.shadow_ram_control == Regs::ShadowRamControl::TrackWithFilter) { | 168 | shadow_state.shadow_ram_control == Regs::ShadowRamControl::TrackWithFilter) { |
| 168 | shadow_state.reg_array[method] = method_call.argument; | 169 | shadow_state.reg_array[method] = arg; |
| 170 | } else if (shadow_state.shadow_ram_control == Regs::ShadowRamControl::Replay) { | ||
| 171 | arg = shadow_state.reg_array[method]; | ||
| 169 | } | 172 | } |
| 170 | 173 | ||
| 171 | if (regs.reg_array[method] != method_call.argument) { | 174 | if (regs.reg_array[method] != arg) { |
| 172 | regs.reg_array[method] = method_call.argument; | 175 | regs.reg_array[method] = arg; |
| 173 | 176 | ||
| 174 | for (const auto& table : dirty.tables) { | 177 | for (const auto& table : dirty.tables) { |
| 175 | dirty.flags[table[method]] = true; | 178 | dirty.flags[table[method]] = true; |
| @@ -182,11 +185,11 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) { | |||
| 182 | break; | 185 | break; |
| 183 | } | 186 | } |
| 184 | case MAXWELL3D_REG_INDEX(macros.data): { | 187 | case MAXWELL3D_REG_INDEX(macros.data): { |
| 185 | ProcessMacroUpload(method_call.argument); | 188 | ProcessMacroUpload(arg); |
| 186 | break; | 189 | break; |
| 187 | } | 190 | } |
| 188 | case MAXWELL3D_REG_INDEX(macros.bind): { | 191 | case MAXWELL3D_REG_INDEX(macros.bind): { |
| 189 | ProcessMacroBind(method_call.argument); | 192 | ProcessMacroBind(arg); |
| 190 | break; | 193 | break; |
| 191 | } | 194 | } |
| 192 | case MAXWELL3D_REG_INDEX(firmware[4]): { | 195 | case MAXWELL3D_REG_INDEX(firmware[4]): { |
| @@ -262,7 +265,7 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) { | |||
| 262 | } | 265 | } |
| 263 | case MAXWELL3D_REG_INDEX(data_upload): { | 266 | case MAXWELL3D_REG_INDEX(data_upload): { |
| 264 | const bool is_last_call = method_call.IsLastCall(); | 267 | const bool is_last_call = method_call.IsLastCall(); |
| 265 | upload_state.ProcessData(method_call.argument, is_last_call); | 268 | upload_state.ProcessData(arg, is_last_call); |
| 266 | if (is_last_call) { | 269 | if (is_last_call) { |
| 267 | OnMemoryWrite(); | 270 | OnMemoryWrite(); |
| 268 | } | 271 | } |