diff options
| author | 2019-04-15 23:05:05 -0400 | |
|---|---|---|
| committer | 2019-04-15 23:10:24 -0400 | |
| commit | ef381e6924ee28162d3ce1cff0523ea7a88981d2 (patch) | |
| tree | 59967fcddc8f7c4586818dea3378c924cd53d426 /src/video_core/engines | |
| parent | GPU MemoryManager: Implement ReadBlockUnsafe and WriteBlockUnsafe (diff) | |
| download | yuzu-ef381e6924ee28162d3ce1cff0523ea7a88981d2.tar.gz yuzu-ef381e6924ee28162d3ce1cff0523ea7a88981d2.tar.xz yuzu-ef381e6924ee28162d3ce1cff0523ea7a88981d2.zip | |
Use ReadBlockUnsafe on TIC and TSC reading
Use ReadBlockUnsafe on TIC and TSC reading as memory is never flushed
from host GPU there.
Diffstat (limited to 'src/video_core/engines')
| -rw-r--r-- | src/video_core/engines/maxwell_3d.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index 74403eed4..69401fcda 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp | |||
| @@ -418,7 +418,7 @@ Texture::TICEntry Maxwell3D::GetTICEntry(u32 tic_index) const { | |||
| 418 | const GPUVAddr tic_address_gpu{regs.tic.TICAddress() + tic_index * sizeof(Texture::TICEntry)}; | 418 | const GPUVAddr tic_address_gpu{regs.tic.TICAddress() + tic_index * sizeof(Texture::TICEntry)}; |
| 419 | 419 | ||
| 420 | Texture::TICEntry tic_entry; | 420 | Texture::TICEntry tic_entry; |
| 421 | memory_manager.ReadBlock(tic_address_gpu, &tic_entry, sizeof(Texture::TICEntry)); | 421 | memory_manager.ReadBlockUnsafe(tic_address_gpu, &tic_entry, sizeof(Texture::TICEntry)); |
| 422 | 422 | ||
| 423 | ASSERT_MSG(tic_entry.header_version == Texture::TICHeaderVersion::BlockLinear || | 423 | ASSERT_MSG(tic_entry.header_version == Texture::TICHeaderVersion::BlockLinear || |
| 424 | tic_entry.header_version == Texture::TICHeaderVersion::Pitch, | 424 | tic_entry.header_version == Texture::TICHeaderVersion::Pitch, |
| @@ -439,7 +439,7 @@ Texture::TSCEntry Maxwell3D::GetTSCEntry(u32 tsc_index) const { | |||
| 439 | const GPUVAddr tsc_address_gpu{regs.tsc.TSCAddress() + tsc_index * sizeof(Texture::TSCEntry)}; | 439 | const GPUVAddr tsc_address_gpu{regs.tsc.TSCAddress() + tsc_index * sizeof(Texture::TSCEntry)}; |
| 440 | 440 | ||
| 441 | Texture::TSCEntry tsc_entry; | 441 | Texture::TSCEntry tsc_entry; |
| 442 | memory_manager.ReadBlock(tsc_address_gpu, &tsc_entry, sizeof(Texture::TSCEntry)); | 442 | memory_manager.ReadBlockUnsafe(tsc_address_gpu, &tsc_entry, sizeof(Texture::TSCEntry)); |
| 443 | return tsc_entry; | 443 | return tsc_entry; |
| 444 | } | 444 | } |
| 445 | 445 | ||