summaryrefslogtreecommitdiff
path: root/src/video_core/engines
diff options
context:
space:
mode:
authorGravatar Subv2018-06-06 23:54:25 -0500
committerGravatar Subv2018-07-03 16:56:44 -0500
commitbe51120d237cb551fae90fbfaebda41669c40403 (patch)
tree37e4ec442f159f6c63ee6db560e4ff23df44bad1 /src/video_core/engines
parentGPU: Added registers for the CLEAR_BUFFERS and CLEAR_COLOR methods. (diff)
downloadyuzu-be51120d237cb551fae90fbfaebda41669c40403.tar.gz
yuzu-be51120d237cb551fae90fbfaebda41669c40403.tar.xz
yuzu-be51120d237cb551fae90fbfaebda41669c40403.zip
GPU: Bind and clear the render target when the CLEAR_BUFFERS register is written to.
Diffstat (limited to 'src/video_core/engines')
-rw-r--r--src/video_core/engines/maxwell_3d.cpp11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 93c43c8cb..78f1c0ea7 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -126,6 +126,10 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
126 DrawArrays(); 126 DrawArrays();
127 break; 127 break;
128 } 128 }
129 case MAXWELL3D_REG_INDEX(clear_buffers): {
130 ProcessClearBuffers();
131 break;
132 }
129 case MAXWELL3D_REG_INDEX(query.query_get): { 133 case MAXWELL3D_REG_INDEX(query.query_get): {
130 ProcessQueryGet(); 134 ProcessQueryGet();
131 break; 135 break;
@@ -415,5 +419,12 @@ bool Maxwell3D::IsShaderStageEnabled(Regs::ShaderStage stage) const {
415 UNREACHABLE(); 419 UNREACHABLE();
416} 420}
417 421
422void Maxwell3D::ProcessClearBuffers() {
423 ASSERT(regs.clear_buffers.R && regs.clear_buffers.G && regs.clear_buffers.B &&
424 regs.clear_buffers.A);
425
426 VideoCore::g_renderer->Rasterizer()->Clear();
427}
428
418} // namespace Engines 429} // namespace Engines
419} // namespace Tegra 430} // namespace Tegra