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authorGravatar bunnei2018-11-23 23:31:04 -0500
committerGravatar GitHub2018-11-23 23:31:04 -0500
commitb6b78203ccbbf5e7f3306e84203448583c3394e6 (patch)
tree4d1aeceb566594e3f396bf686524b29d06b62c42 /src/video_core/engines
parentMerge pull request #1744 from degasus/shader_cache (diff)
parentgl_shader_decompiler: Add a message for unimplemented cc generation (diff)
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Merge pull request #1769 from ReinUsesLisp/cc
gl_shader_decompiler: Rename cc to condition code and name internal flags
Diffstat (limited to 'src/video_core/engines')
-rw-r--r--src/video_core/engines/shader_bytecode.h7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index c5f502ce1..7e8449bc4 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -262,7 +262,7 @@ enum class FlowCondition : u64 {
262 Fcsm_Tr = 0x1C, // TODO(bunnei): What is this used for? 262 Fcsm_Tr = 0x1C, // TODO(bunnei): What is this used for?
263}; 263};
264 264
265enum class ControlCode : u64 { 265enum class ConditionCode : u64 {
266 F = 0, 266 F = 0,
267 LT = 1, 267 LT = 1,
268 EQ = 2, 268 EQ = 2,
@@ -570,7 +570,6 @@ union Instruction {
570 BitField<39, 2, u64> tab5cb8_2; 570 BitField<39, 2, u64> tab5cb8_2;
571 BitField<41, 3, u64> tab5c68_1; 571 BitField<41, 3, u64> tab5c68_1;
572 BitField<44, 2, u64> tab5c68_0; 572 BitField<44, 2, u64> tab5c68_0;
573 BitField<47, 1, u64> cc;
574 BitField<48, 1, u64> negate_b; 573 BitField<48, 1, u64> negate_b;
575 } fmul; 574 } fmul;
576 575
@@ -832,7 +831,7 @@ union Instruction {
832 union { 831 union {
833 BitField<0, 3, u64> pred0; 832 BitField<0, 3, u64> pred0;
834 BitField<3, 3, u64> pred3; 833 BitField<3, 3, u64> pred3;
835 BitField<8, 5, ControlCode> cc; // flag in cc 834 BitField<8, 5, ConditionCode> cc; // flag in cc
836 BitField<39, 3, u64> pred39; 835 BitField<39, 3, u64> pred39;
837 BitField<42, 1, u64> neg_pred39; 836 BitField<42, 1, u64> neg_pred39;
838 BitField<45, 4, PredOperation> op; // op with pred39 837 BitField<45, 4, PredOperation> op; // op with pred39
@@ -1236,7 +1235,7 @@ union Instruction {
1236 BitField<60, 1, u64> is_b_gpr; 1235 BitField<60, 1, u64> is_b_gpr;
1237 BitField<59, 1, u64> is_c_gpr; 1236 BitField<59, 1, u64> is_c_gpr;
1238 BitField<20, 24, s64> smem_imm; 1237 BitField<20, 24, s64> smem_imm;
1239 BitField<0, 5, ControlCode> flow_control_code; 1238 BitField<0, 5, ConditionCode> flow_condition_code;
1240 1239
1241 Attribute attribute; 1240 Attribute attribute;
1242 Sampler sampler; 1241 Sampler sampler;