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| author | 2018-10-31 22:34:18 -0400 | |
|---|---|---|
| committer | 2018-10-31 22:34:18 -0400 | |
| commit | 86e70cf30210c6a43b23884012cc5e24fff68d03 (patch) | |
| tree | a22222e4a592003f2d9b276f17e28e5ff0a78e26 /src/video_core/engines | |
| parent | Merge pull request #1614 from ReinUsesLisp/surface-params (diff) | |
| parent | Assert Control Codes Generation (diff) | |
| download | yuzu-86e70cf30210c6a43b23884012cc5e24fff68d03.tar.gz yuzu-86e70cf30210c6a43b23884012cc5e24fff68d03.tar.xz yuzu-86e70cf30210c6a43b23884012cc5e24fff68d03.zip | |
Merge pull request #1528 from FernandoS27/assert-control-codes
Assert Control Codes Generation on Shader Instructions
Diffstat (limited to 'src/video_core/engines')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index b84da512f..27c011e6f 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -578,6 +578,10 @@ union Instruction { | |||
| 578 | } fmul32; | 578 | } fmul32; |
| 579 | 579 | ||
| 580 | union { | 580 | union { |
| 581 | BitField<52, 1, u64> generates_cc; | ||
| 582 | } op_32; | ||
| 583 | |||
| 584 | union { | ||
| 581 | BitField<48, 1, u64> is_signed; | 585 | BitField<48, 1, u64> is_signed; |
| 582 | } shift; | 586 | } shift; |
| 583 | 587 | ||
| @@ -1658,4 +1662,4 @@ private: | |||
| 1658 | } | 1662 | } |
| 1659 | }; | 1663 | }; |
| 1660 | 1664 | ||
| 1661 | } // namespace Tegra::Shader \ No newline at end of file | 1665 | } // namespace Tegra::Shader |