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authorGravatar Subv2018-02-11 23:44:12 -0500
committerGravatar Subv2018-02-11 23:44:12 -0500
commit6cddf9d88e7fc49919fda92bcd4235797c56f07f (patch)
tree3f7da3795b5561b2d325325b72610996e2857742 /src/video_core/engines
parentGPU: Added a command processor to decode the GPU pushbuffers and forward the ... (diff)
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Make a GPU class in VideoCore to contain the GPU state.
Also moved the GPU MemoryManager class to video_core since it makes more sense for it to be there.
Diffstat (limited to 'src/video_core/engines')
-rw-r--r--src/video_core/engines/fermi_2d.cpp4
-rw-r--r--src/video_core/engines/fermi_2d.h10
-rw-r--r--src/video_core/engines/maxwell_3d.cpp4
-rw-r--r--src/video_core/engines/maxwell_3d.h10
-rw-r--r--src/video_core/engines/maxwell_compute.cpp4
-rw-r--r--src/video_core/engines/maxwell_compute.h10
6 files changed, 24 insertions, 18 deletions
diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp
index 3d62c321f..7aab163dc 100644
--- a/src/video_core/engines/fermi_2d.cpp
+++ b/src/video_core/engines/fermi_2d.cpp
@@ -6,10 +6,8 @@
6 6
7namespace Tegra { 7namespace Tegra {
8namespace Engines { 8namespace Engines {
9namespace Fermi2D {
10 9
11void WriteReg(u32 method, u32 value) {} 10void Fermi2D::WriteReg(u32 method, u32 value) {}
12 11
13} // namespace Fermi2D
14} // namespace Engines 12} // namespace Engines
15} // namespace Tegra 13} // namespace Tegra
diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index 6f3f5dfbc..8967ddede 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -8,11 +8,15 @@
8 8
9namespace Tegra { 9namespace Tegra {
10namespace Engines { 10namespace Engines {
11namespace Fermi2D {
12 11
13void WriteReg(u32 method, u32 value); 12class Fermi2D final {
13public:
14 Fermi2D() = default;
15 ~Fermi2D() = default;
14 16
15} // namespace Fermi2D 17 /// Write the value to the register identified by method.
18 void WriteReg(u32 method, u32 value);
19};
16 20
17} // namespace Engines 21} // namespace Engines
18} // namespace Tegra 22} // namespace Tegra
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index c2697c960..ccdb310f0 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -6,10 +6,8 @@
6 6
7namespace Tegra { 7namespace Tegra {
8namespace Engines { 8namespace Engines {
9namespace Maxwell3D {
10 9
11void WriteReg(u32 method, u32 value) {} 10void Maxwell3D::WriteReg(u32 method, u32 value) {}
12 11
13} // namespace Maxwell3D
14} // namespace Engines 12} // namespace Engines
15} // namespace Tegra 13} // namespace Tegra
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 6957fb721..0f4ae1328 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -8,11 +8,15 @@
8 8
9namespace Tegra { 9namespace Tegra {
10namespace Engines { 10namespace Engines {
11namespace Maxwell3D {
12 11
13void WriteReg(u32 method, u32 value); 12class Maxwell3D final {
13public:
14 Maxwell3D() = default;
15 ~Maxwell3D() = default;
14 16
15} // namespace Maxwell3D 17 /// Write the value to the register identified by method.
18 void WriteReg(u32 method, u32 value);
19};
16 20
17} // namespace Engines 21} // namespace Engines
18} // namespace Tegra 22} // namespace Tegra
diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp
index c2134d63b..e4e5f9e5e 100644
--- a/src/video_core/engines/maxwell_compute.cpp
+++ b/src/video_core/engines/maxwell_compute.cpp
@@ -6,10 +6,8 @@
6 6
7namespace Tegra { 7namespace Tegra {
8namespace Engines { 8namespace Engines {
9namespace MaxwellCompute {
10 9
11void WriteReg(u32 method, u32 value) {} 10void MaxwellCompute::WriteReg(u32 method, u32 value) {}
12 11
13} // namespace MaxwellCompute
14} // namespace Engines 12} // namespace Engines
15} // namespace Tegra 13} // namespace Tegra
diff --git a/src/video_core/engines/maxwell_compute.h b/src/video_core/engines/maxwell_compute.h
index dc9a13593..7262e1bcb 100644
--- a/src/video_core/engines/maxwell_compute.h
+++ b/src/video_core/engines/maxwell_compute.h
@@ -8,11 +8,15 @@
8 8
9namespace Tegra { 9namespace Tegra {
10namespace Engines { 10namespace Engines {
11namespace MaxwellCompute {
12 11
13void WriteReg(u32 method, u32 value); 12class MaxwellCompute final {
13public:
14 MaxwellCompute() = default;
15 ~MaxwellCompute() = default;
14 16
15} // namespace MaxwellCompute 17 /// Write the value to the register identified by method.
18 void WriteReg(u32 method, u32 value);
19};
16 20
17} // namespace Engines 21} // namespace Engines
18} // namespace Tegra 22} // namespace Tegra