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| author | 2018-06-05 22:01:29 -0400 | |
|---|---|---|
| committer | 2018-06-05 22:01:29 -0400 | |
| commit | 5fb99e6a166786eab5e1f8c656fe8431b3e11255 (patch) | |
| tree | f9a689d4c732095234417560247a32622df39be8 /src/video_core/engines | |
| parent | Merge pull request #523 from yuzu-emu/revert-507-3616 (diff) | |
| parent | GPU: Implemented the F2I_R shader instruction. (diff) | |
| download | yuzu-5fb99e6a166786eab5e1f8c656fe8431b3e11255.tar.gz yuzu-5fb99e6a166786eab5e1f8c656fe8431b3e11255.tar.xz yuzu-5fb99e6a166786eab5e1f8c656fe8431b3e11255.zip | |
Merge pull request #516 from Subv/f2i_r
GPU: Implemented the F2I_R shader instruction.
Diffstat (limited to 'src/video_core/engines')
| -rw-r--r-- | src/video_core/engines/shader_bytecode.h | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 38757c038..4eb507325 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h | |||
| @@ -173,6 +173,13 @@ enum class SubOp : u64 { | |||
| 173 | Min = 0x8, | 173 | Min = 0x8, |
| 174 | }; | 174 | }; |
| 175 | 175 | ||
| 176 | enum class FloatRoundingOp : u64 { | ||
| 177 | None = 0, | ||
| 178 | Floor = 1, | ||
| 179 | Ceil = 2, | ||
| 180 | Trunc = 3, | ||
| 181 | }; | ||
| 182 | |||
| 176 | union Instruction { | 183 | union Instruction { |
| 177 | Instruction& operator=(const Instruction& instr) { | 184 | Instruction& operator=(const Instruction& instr) { |
| 178 | value = instr.value; | 185 | value = instr.value; |
| @@ -290,11 +297,20 @@ union Instruction { | |||
| 290 | 297 | ||
| 291 | union { | 298 | union { |
| 292 | BitField<10, 2, Register::Size> size; | 299 | BitField<10, 2, Register::Size> size; |
| 293 | BitField<13, 1, u64> is_signed; | 300 | BitField<12, 1, u64> is_output_signed; |
| 301 | BitField<13, 1, u64> is_input_signed; | ||
| 294 | BitField<41, 2, u64> selector; | 302 | BitField<41, 2, u64> selector; |
| 295 | BitField<45, 1, u64> negate_a; | 303 | BitField<45, 1, u64> negate_a; |
| 296 | BitField<49, 1, u64> abs_a; | 304 | BitField<49, 1, u64> abs_a; |
| 297 | BitField<50, 1, u64> saturate_a; | 305 | BitField<50, 1, u64> saturate_a; |
| 306 | |||
| 307 | union { | ||
| 308 | BitField<39, 2, FloatRoundingOp> rounding; | ||
| 309 | } f2i; | ||
| 310 | |||
| 311 | union { | ||
| 312 | BitField<39, 4, u64> rounding; | ||
| 313 | } f2f; | ||
| 298 | } conversion; | 314 | } conversion; |
| 299 | 315 | ||
| 300 | union { | 316 | union { |
| @@ -560,9 +576,9 @@ private: | |||
| 560 | INST("0100110010101---", Id::F2F_C, Type::Conversion, "F2F_C"), | 576 | INST("0100110010101---", Id::F2F_C, Type::Conversion, "F2F_C"), |
| 561 | INST("0101110010101---", Id::F2F_R, Type::Conversion, "F2F_R"), | 577 | INST("0101110010101---", Id::F2F_R, Type::Conversion, "F2F_R"), |
| 562 | INST("0011100-10101---", Id::F2F_IMM, Type::Conversion, "F2F_IMM"), | 578 | INST("0011100-10101---", Id::F2F_IMM, Type::Conversion, "F2F_IMM"), |
| 563 | INST("0100110010110---", Id::F2I_C, Type::Arithmetic, "F2I_C"), | 579 | INST("0100110010110---", Id::F2I_C, Type::Conversion, "F2I_C"), |
| 564 | INST("0101110010110---", Id::F2I_R, Type::Arithmetic, "F2I_R"), | 580 | INST("0101110010110---", Id::F2I_R, Type::Conversion, "F2I_R"), |
| 565 | INST("0011100-10110---", Id::F2I_IMM, Type::Arithmetic, "F2I_IMM"), | 581 | INST("0011100-10110---", Id::F2I_IMM, Type::Conversion, "F2I_IMM"), |
| 566 | INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"), | 582 | INST("0100110010011---", Id::MOV_C, Type::Arithmetic, "MOV_C"), |
| 567 | INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"), | 583 | INST("0101110010011---", Id::MOV_R, Type::Arithmetic, "MOV_R"), |
| 568 | INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"), | 584 | INST("0011100-10011---", Id::MOV_IMM, Type::Arithmetic, "MOV_IMM"), |