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| author | 2022-10-11 17:22:40 -0400 | |
|---|---|---|
| committer | 2022-10-11 17:22:40 -0400 | |
| commit | 133a68ee9b420d30a58fe7ddd8c03065324a4d70 (patch) | |
| tree | e2a8f89c372b545c6cabbcc53a9d725a6fe2cdb1 /src/video_core/engines | |
| parent | Merge pull request #9044 from lat9nq/mingw-gcc-revert (diff) | |
| parent | Fix stencil func registers, make clip control equivalent to how it was before... (diff) | |
| download | yuzu-133a68ee9b420d30a58fe7ddd8c03065324a4d70.tar.gz yuzu-133a68ee9b420d30a58fe7ddd8c03065324a4d70.tar.xz yuzu-133a68ee9b420d30a58fe7ddd8c03065324a4d70.zip | |
Merge pull request #9048 from Kelebek1/regs
[video_core] Fix stencil mask registers
Diffstat (limited to 'src/video_core/engines')
| -rw-r--r-- | src/video_core/engines/maxwell_3d.cpp | 8 | ||||
| -rw-r--r-- | src/video_core/engines/maxwell_3d.h | 22 |
2 files changed, 16 insertions, 14 deletions
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index 84c1abf3d..89a9d1f5a 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp | |||
| @@ -74,15 +74,15 @@ void Maxwell3D::InitializeRegisterDefaults() { | |||
| 74 | regs.stencil_front_op.zfail = Regs::StencilOp::Op::Keep_D3D; | 74 | regs.stencil_front_op.zfail = Regs::StencilOp::Op::Keep_D3D; |
| 75 | regs.stencil_front_op.zpass = Regs::StencilOp::Op::Keep_D3D; | 75 | regs.stencil_front_op.zpass = Regs::StencilOp::Op::Keep_D3D; |
| 76 | regs.stencil_front_op.func = Regs::ComparisonOp::Always_GL; | 76 | regs.stencil_front_op.func = Regs::ComparisonOp::Always_GL; |
| 77 | regs.stencil_front_func.func_mask = 0xFFFFFFFF; | 77 | regs.stencil_front_func_mask = 0xFFFFFFFF; |
| 78 | regs.stencil_front_func.mask = 0xFFFFFFFF; | 78 | regs.stencil_front_mask = 0xFFFFFFFF; |
| 79 | regs.stencil_two_side_enable = 1; | 79 | regs.stencil_two_side_enable = 1; |
| 80 | regs.stencil_back_op.fail = Regs::StencilOp::Op::Keep_D3D; | 80 | regs.stencil_back_op.fail = Regs::StencilOp::Op::Keep_D3D; |
| 81 | regs.stencil_back_op.zfail = Regs::StencilOp::Op::Keep_D3D; | 81 | regs.stencil_back_op.zfail = Regs::StencilOp::Op::Keep_D3D; |
| 82 | regs.stencil_back_op.zpass = Regs::StencilOp::Op::Keep_D3D; | 82 | regs.stencil_back_op.zpass = Regs::StencilOp::Op::Keep_D3D; |
| 83 | regs.stencil_back_op.func = Regs::ComparisonOp::Always_GL; | 83 | regs.stencil_back_op.func = Regs::ComparisonOp::Always_GL; |
| 84 | regs.stencil_back_func.func_mask = 0xFFFFFFFF; | 84 | regs.stencil_back_func_mask = 0xFFFFFFFF; |
| 85 | regs.stencil_back_func.mask = 0xFFFFFFFF; | 85 | regs.stencil_back_mask = 0xFFFFFFFF; |
| 86 | 86 | ||
| 87 | regs.depth_test_func = Regs::ComparisonOp::Always_GL; | 87 | regs.depth_test_func = Regs::ComparisonOp::Always_GL; |
| 88 | regs.gl_front_face = Regs::FrontFace::CounterClockWise; | 88 | regs.gl_front_face = Regs::FrontFace::CounterClockWise; |
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index efe1073b0..12dbd9cc4 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h | |||
| @@ -1795,12 +1795,6 @@ public: | |||
| 1795 | ComparisonOp func; | 1795 | ComparisonOp func; |
| 1796 | }; | 1796 | }; |
| 1797 | 1797 | ||
| 1798 | struct StencilFunc { | ||
| 1799 | s32 ref; | ||
| 1800 | u32 func_mask; | ||
| 1801 | u32 mask; | ||
| 1802 | }; | ||
| 1803 | |||
| 1804 | struct PsSaturate { | 1798 | struct PsSaturate { |
| 1805 | // Opposite of DepthMode | 1799 | // Opposite of DepthMode |
| 1806 | enum class Depth : u32 { | 1800 | enum class Depth : u32 { |
| @@ -2737,7 +2731,9 @@ public: | |||
| 2737 | u32 post_z_pixel_imask; ///< 0x0F1C | 2731 | u32 post_z_pixel_imask; ///< 0x0F1C |
| 2738 | INSERT_PADDING_BYTES_NOINIT(0x20); | 2732 | INSERT_PADDING_BYTES_NOINIT(0x20); |
| 2739 | ConstantColorRendering const_color_rendering; ///< 0x0F40 | 2733 | ConstantColorRendering const_color_rendering; ///< 0x0F40 |
| 2740 | StencilFunc stencil_back_func; ///< 0x0F54 | 2734 | s32 stencil_back_ref; ///< 0x0F54 |
| 2735 | u32 stencil_back_mask; ///< 0x0F58 | ||
| 2736 | u32 stencil_back_func_mask; ///< 0x0F5C | ||
| 2741 | INSERT_PADDING_BYTES_NOINIT(0x24); | 2737 | INSERT_PADDING_BYTES_NOINIT(0x24); |
| 2742 | VertexStreamSubstitute vertex_stream_substitute; ///< 0x0F84 | 2738 | VertexStreamSubstitute vertex_stream_substitute; ///< 0x0F84 |
| 2743 | u32 line_mode_clip_generated_edge_do_not_draw; ///< 0x0F8C | 2739 | u32 line_mode_clip_generated_edge_do_not_draw; ///< 0x0F8C |
| @@ -2855,7 +2851,9 @@ public: | |||
| 2855 | Blend blend; ///< 0x133C | 2851 | Blend blend; ///< 0x133C |
| 2856 | u32 stencil_enable; ///< 0x1380 | 2852 | u32 stencil_enable; ///< 0x1380 |
| 2857 | StencilOp stencil_front_op; ///< 0x1384 | 2853 | StencilOp stencil_front_op; ///< 0x1384 |
| 2858 | StencilFunc stencil_front_func; ///< 0x1394 | 2854 | s32 stencil_front_ref; ///< 0x1394 |
| 2855 | s32 stencil_front_func_mask; ///< 0x1398 | ||
| 2856 | s32 stencil_front_mask; ///< 0x139C | ||
| 2859 | INSERT_PADDING_BYTES_NOINIT(0x4); | 2857 | INSERT_PADDING_BYTES_NOINIT(0x4); |
| 2860 | u32 draw_auto_start_byte_count; ///< 0x13A4 | 2858 | u32 draw_auto_start_byte_count; ///< 0x13A4 |
| 2861 | PsSaturate frag_color_clamp; ///< 0x13A8 | 2859 | PsSaturate frag_color_clamp; ///< 0x13A8 |
| @@ -3311,7 +3309,9 @@ ASSERT_REG_POSITION(vpc_perf, 0x0F14); | |||
| 3311 | ASSERT_REG_POSITION(pm_local_trigger, 0x0F18); | 3309 | ASSERT_REG_POSITION(pm_local_trigger, 0x0F18); |
| 3312 | ASSERT_REG_POSITION(post_z_pixel_imask, 0x0F1C); | 3310 | ASSERT_REG_POSITION(post_z_pixel_imask, 0x0F1C); |
| 3313 | ASSERT_REG_POSITION(const_color_rendering, 0x0F40); | 3311 | ASSERT_REG_POSITION(const_color_rendering, 0x0F40); |
| 3314 | ASSERT_REG_POSITION(stencil_back_func, 0x0F54); | 3312 | ASSERT_REG_POSITION(stencil_back_ref, 0x0F54); |
| 3313 | ASSERT_REG_POSITION(stencil_back_mask, 0x0F58); | ||
| 3314 | ASSERT_REG_POSITION(stencil_back_func_mask, 0x0F5C); | ||
| 3315 | ASSERT_REG_POSITION(vertex_stream_substitute, 0x0F84); | 3315 | ASSERT_REG_POSITION(vertex_stream_substitute, 0x0F84); |
| 3316 | ASSERT_REG_POSITION(line_mode_clip_generated_edge_do_not_draw, 0x0F8C); | 3316 | ASSERT_REG_POSITION(line_mode_clip_generated_edge_do_not_draw, 0x0F8C); |
| 3317 | ASSERT_REG_POSITION(color_mask_common, 0x0F90); | 3317 | ASSERT_REG_POSITION(color_mask_common, 0x0F90); |
| @@ -3416,7 +3416,9 @@ ASSERT_REG_POSITION(invalidate_texture_data_cache_lines, 0x1338); | |||
| 3416 | ASSERT_REG_POSITION(blend, 0x133C); | 3416 | ASSERT_REG_POSITION(blend, 0x133C); |
| 3417 | ASSERT_REG_POSITION(stencil_enable, 0x1380); | 3417 | ASSERT_REG_POSITION(stencil_enable, 0x1380); |
| 3418 | ASSERT_REG_POSITION(stencil_front_op, 0x1384); | 3418 | ASSERT_REG_POSITION(stencil_front_op, 0x1384); |
| 3419 | ASSERT_REG_POSITION(stencil_front_func, 0x1394); | 3419 | ASSERT_REG_POSITION(stencil_front_ref, 0x1394); |
| 3420 | ASSERT_REG_POSITION(stencil_front_func_mask, 0x1398); | ||
| 3421 | ASSERT_REG_POSITION(stencil_front_mask, 0x139C); | ||
| 3420 | ASSERT_REG_POSITION(draw_auto_start_byte_count, 0x13A4); | 3422 | ASSERT_REG_POSITION(draw_auto_start_byte_count, 0x13A4); |
| 3421 | ASSERT_REG_POSITION(frag_color_clamp, 0x13A8); | 3423 | ASSERT_REG_POSITION(frag_color_clamp, 0x13A8); |
| 3422 | ASSERT_REG_POSITION(window_origin, 0x13AC); | 3424 | ASSERT_REG_POSITION(window_origin, 0x13AC); |