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authorGravatar ameerj2020-11-23 15:01:40 -0500
committerGravatar ameerj2021-02-13 13:07:53 -0500
commit77564f987cc52ea6d841e7d18ade2646783f3651 (patch)
tree6c21f3c58453d3af5fba62b1fa59266d1149c180 /src/video_core/cdma_pusher.h
parentnvdec cleanup (diff)
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streamline cdma_pusher/command_classes
Diffstat (limited to 'src/video_core/cdma_pusher.h')
-rw-r--r--src/video_core/cdma_pusher.h14
1 files changed, 4 insertions, 10 deletions
diff --git a/src/video_core/cdma_pusher.h b/src/video_core/cdma_pusher.h
index de7a3a35b..e16eb2254 100644
--- a/src/video_core/cdma_pusher.h
+++ b/src/video_core/cdma_pusher.h
@@ -48,16 +48,10 @@ enum class ChClassId : u32 {
48 NvDec = 0xf0 48 NvDec = 0xf0
49}; 49};
50 50
51enum class ChMethod : u32 {
52 Empty = 0,
53 SetMethod = 0x10,
54 SetData = 0x11,
55};
56
57union ChCommandHeader { 51union ChCommandHeader {
58 u32 raw; 52 u32 raw;
59 BitField<0, 16, u32> value; 53 BitField<0, 16, u32> value;
60 BitField<16, 12, ChMethod> method_offset; 54 BitField<16, 12, u32> method_offset;
61 BitField<28, 4, ChSubmissionMode> submission_mode; 55 BitField<28, 4, ChSubmissionMode> submission_mode;
62}; 56};
63static_assert(sizeof(ChCommandHeader) == sizeof(u32), "ChCommand header is an invalid size"); 57static_assert(sizeof(ChCommandHeader) == sizeof(u32), "ChCommand header is an invalid size");
@@ -107,7 +101,7 @@ private:
107 void ExecuteCommand(u32 state_offset, u32 data); 101 void ExecuteCommand(u32 state_offset, u32 data);
108 102
109 /// Write arguments value to the ThiRegisters member at the specified offset 103 /// Write arguments value to the ThiRegisters member at the specified offset
110 void ThiStateWrite(ThiRegisters& state, u32 state_offset, const std::vector<u32>& arguments); 104 void ThiStateWrite(ThiRegisters& state, u32 offset, u32 argument);
111 105
112 GPU& gpu; 106 GPU& gpu;
113 std::shared_ptr<Tegra::Nvdec> nvdec_processor; 107 std::shared_ptr<Tegra::Nvdec> nvdec_processor;
@@ -118,8 +112,8 @@ private:
118 ThiRegisters vic_thi_state{}; 112 ThiRegisters vic_thi_state{};
119 ThiRegisters nvdec_thi_state{}; 113 ThiRegisters nvdec_thi_state{};
120 114
121 s32 count{}; 115 u32 count{};
122 s32 offset{}; 116 u32 offset{};
123 u32 mask{}; 117 u32 mask{};
124 bool incrementing{}; 118 bool incrementing{};
125}; 119};