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| author | 2022-01-30 22:26:01 +0100 | |
|---|---|---|
| committer | 2022-10-06 21:00:52 +0200 | |
| commit | 2931101e6f5aa755566ef40f6e6dc71909fd3e92 (patch) | |
| tree | 76e847786e355e24a136562d42177b895a03315e /src/video_core/cdma_pusher.h | |
| parent | VideoCore: Refactor syncing. (diff) | |
| download | yuzu-2931101e6f5aa755566ef40f6e6dc71909fd3e92.tar.gz yuzu-2931101e6f5aa755566ef40f6e6dc71909fd3e92.tar.xz yuzu-2931101e6f5aa755566ef40f6e6dc71909fd3e92.zip | |
NVDRV: Refactor Host1x
Diffstat (limited to 'src/video_core/cdma_pusher.h')
| -rw-r--r-- | src/video_core/cdma_pusher.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/video_core/cdma_pusher.h b/src/video_core/cdma_pusher.h index de17c2082..83112dfce 100644 --- a/src/video_core/cdma_pusher.h +++ b/src/video_core/cdma_pusher.h | |||
| @@ -12,10 +12,9 @@ | |||
| 12 | 12 | ||
| 13 | namespace Tegra { | 13 | namespace Tegra { |
| 14 | 14 | ||
| 15 | class GPU; | ||
| 16 | |||
| 17 | namespace Host1x { | 15 | namespace Host1x { |
| 18 | class Control; | 16 | class Control; |
| 17 | class Host1x; | ||
| 19 | class Nvdec; | 18 | class Nvdec; |
| 20 | class SyncptIncrManager; | 19 | class SyncptIncrManager; |
| 21 | class Vic; | 20 | class Vic; |
| @@ -91,7 +90,7 @@ enum class ThiMethod : u32 { | |||
| 91 | 90 | ||
| 92 | class CDmaPusher { | 91 | class CDmaPusher { |
| 93 | public: | 92 | public: |
| 94 | explicit CDmaPusher(GPU& gpu_); | 93 | explicit CDmaPusher(Host1x::Host1x& host1x); |
| 95 | ~CDmaPusher(); | 94 | ~CDmaPusher(); |
| 96 | 95 | ||
| 97 | /// Process the command entry | 96 | /// Process the command entry |
| @@ -104,7 +103,7 @@ private: | |||
| 104 | /// Write arguments value to the ThiRegisters member at the specified offset | 103 | /// Write arguments value to the ThiRegisters member at the specified offset |
| 105 | void ThiStateWrite(ThiRegisters& state, u32 offset, u32 argument); | 104 | void ThiStateWrite(ThiRegisters& state, u32 offset, u32 argument); |
| 106 | 105 | ||
| 107 | GPU& gpu; | 106 | Host1x::Host1x& host1x; |
| 108 | std::shared_ptr<Tegra::Host1x::Nvdec> nvdec_processor; | 107 | std::shared_ptr<Tegra::Host1x::Nvdec> nvdec_processor; |
| 109 | std::unique_ptr<Tegra::Host1x::Vic> vic_processor; | 108 | std::unique_ptr<Tegra::Host1x::Vic> vic_processor; |
| 110 | std::unique_ptr<Tegra::Host1x::Control> host1x_processor; | 109 | std::unique_ptr<Tegra::Host1x::Control> host1x_processor; |