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| author | 2021-04-27 21:05:41 -0400 | |
|---|---|---|
| committer | 2021-07-22 21:51:29 -0400 | |
| commit | fb14820c86f082f970183c2722c5c38bcbb5a2ab (patch) | |
| tree | 7126d5473e05545e923314e7f91f10e0137eb730 /src/shader_recompiler | |
| parent | vk_scheduler: Allow command submission on worker thread (diff) | |
| download | yuzu-fb14820c86f082f970183c2722c5c38bcbb5a2ab.tar.gz yuzu-fb14820c86f082f970183c2722c5c38bcbb5a2ab.tar.xz yuzu-fb14820c86f082f970183c2722c5c38bcbb5a2ab.zip | |
shader: Fix IADD3.CC
Diffstat (limited to 'src/shader_recompiler')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp | 17 |
1 files changed, 5 insertions, 12 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp index 15da90365..259a6e6ac 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_add_three_input.cpp | |||
| @@ -73,21 +73,13 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) { | |||
| 73 | op_c = v.ir.INeg(op_c); | 73 | op_c = v.ir.INeg(op_c); |
| 74 | } | 74 | } |
| 75 | 75 | ||
| 76 | IR::U32 lhs{v.ir.IAdd(op_a, op_b)}; | 76 | IR::U32 lhs_1{v.ir.IAdd(op_a, op_b)}; |
| 77 | IR::U1 of_1; | ||
| 78 | if (iadd3.cc != 0) { | ||
| 79 | of_1 = v.ir.GetOverflowFromOp(lhs); | ||
| 80 | } | ||
| 81 | if (iadd3.x != 0) { | 77 | if (iadd3.x != 0) { |
| 82 | const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))}; | 78 | const IR::U32 carry{v.ir.Select(v.ir.GetCFlag(), v.ir.Imm32(1), v.ir.Imm32(0))}; |
| 83 | lhs = v.ir.IAdd(lhs, carry); | 79 | lhs_1 = v.ir.IAdd(lhs_1, carry); |
| 84 | } | ||
| 85 | if (iadd3.cc != 0 && iadd3.shift == Shift::Left) { | ||
| 86 | const IR::U32 high_bits{v.ir.ShiftRightLogical(lhs, v.ir.Imm32(16))}; | ||
| 87 | of_1 = v.ir.LogicalOr(of_1, v.ir.INotEqual(v.ir.Imm32(0), high_bits)); | ||
| 88 | } | 80 | } |
| 89 | lhs = IntegerShift(v.ir, lhs, iadd3.shift); | 81 | const IR::U32 lhs_2{IntegerShift(v.ir, lhs_1, iadd3.shift)}; |
| 90 | const IR::U32 result{v.ir.IAdd(lhs, op_c)}; | 82 | const IR::U32 result{v.ir.IAdd(lhs_2, op_c)}; |
| 91 | 83 | ||
| 92 | v.X(iadd3.dest_reg, result); | 84 | v.X(iadd3.dest_reg, result); |
| 93 | if (iadd3.cc != 0) { | 85 | if (iadd3.cc != 0) { |
| @@ -98,6 +90,7 @@ void IADD3(TranslatorVisitor& v, u64 insn, IR::U32 op_b, IR::U32 op_c) { | |||
| 98 | v.SetZFlag(v.ir.GetZeroFromOp(result)); | 90 | v.SetZFlag(v.ir.GetZeroFromOp(result)); |
| 99 | v.SetSFlag(v.ir.GetSignFromOp(result)); | 91 | v.SetSFlag(v.ir.GetSignFromOp(result)); |
| 100 | v.SetCFlag(v.ir.GetCarryFromOp(result)); | 92 | v.SetCFlag(v.ir.GetCarryFromOp(result)); |
| 93 | const IR::U1 of_1{v.ir.ILessThan(lhs_1, op_a, false)}; | ||
| 101 | v.SetOFlag(v.ir.LogicalOr(v.ir.GetOverflowFromOp(result), of_1)); | 94 | v.SetOFlag(v.ir.LogicalOr(v.ir.GetOverflowFromOp(result), of_1)); |
| 102 | } | 95 | } |
| 103 | } | 96 | } |