diff options
| author | 2021-05-09 22:43:29 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:31 -0400 | |
| commit | ad61b47f80b96436ef675abcf1123668d9c1180d (patch) | |
| tree | 555fb6be6058322eae22e7088e8fbc4a615f796d /src/shader_recompiler | |
| parent | glasm: Add fp min/max insts and fix store for fp64 on GLASM (diff) | |
| download | yuzu-ad61b47f80b96436ef675abcf1123668d9c1180d.tar.gz yuzu-ad61b47f80b96436ef675abcf1123668d9c1180d.tar.xz yuzu-ad61b47f80b96436ef675abcf1123668d9c1180d.zip | |
glasm: Add conversion instructions to GLASM
Diffstat (limited to 'src/shader_recompiler')
9 files changed, 351 insertions, 282 deletions
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm.cpp b/src/shader_recompiler/backend/glasm/emit_glasm.cpp index 9db6eb4a0..0e4b189c9 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm.cpp | |||
| @@ -59,6 +59,9 @@ struct RegWrapper { | |||
| 59 | case Type::F32: | 59 | case Type::F32: |
| 60 | ctx.Add("MOV.F {}.x,{};", reg, value.imm_f32); | 60 | ctx.Add("MOV.F {}.x,{};", reg, value.imm_f32); |
| 61 | break; | 61 | break; |
| 62 | case Type::U64: | ||
| 63 | ctx.Add("MOV.U64 {}.x,{};", reg, value.imm_u64); | ||
| 64 | break; | ||
| 62 | case Type::F64: | 65 | case Type::F64: |
| 63 | ctx.Add("MOV.F64 {}.x,{};", reg, value.imm_f64); | 66 | ctx.Add("MOV.F64 {}.x,{};", reg, value.imm_f64); |
| 64 | break; | 67 | break; |
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_bitwise_conversion.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_bitwise_conversion.cpp index eb6140954..a6c66b826 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_bitwise_conversion.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm_bitwise_conversion.cpp | |||
| @@ -48,12 +48,12 @@ void EmitBitCastF64U64(EmitContext&, IR::Inst& inst, const IR::Value& value) { | |||
| 48 | Alias(inst, value); | 48 | Alias(inst, value); |
| 49 | } | 49 | } |
| 50 | 50 | ||
| 51 | void EmitPackUint2x32([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 51 | void EmitPackUint2x32(EmitContext& ctx, IR::Inst& inst, Register value) { |
| 52 | throw NotImplementedException("GLASM instruction"); | 52 | ctx.LongAdd("PK64.U {}.x,{};", inst, value); |
| 53 | } | 53 | } |
| 54 | 54 | ||
| 55 | void EmitUnpackUint2x32([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 55 | void EmitUnpackUint2x32(EmitContext& ctx, IR::Inst& inst, Register value) { |
| 56 | throw NotImplementedException("GLASM instruction"); | 56 | ctx.Add("UP64.U {}.xy,{}.x;", inst, value); |
| 57 | } | 57 | } |
| 58 | 58 | ||
| 59 | void EmitPackFloat2x16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 59 | void EmitPackFloat2x16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { |
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_convert.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_convert.cpp index e69de29bb..ccdf1cbc8 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_convert.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm_convert.cpp | |||
| @@ -0,0 +1,231 @@ | |||
| 1 | // Copyright 2021 yuzu Emulator Project | ||
| 2 | // Licensed under GPLv2 or any later version | ||
| 3 | // Refer to the license.txt file included. | ||
| 4 | |||
| 5 | #include <string_view> | ||
| 6 | |||
| 7 | #include "shader_recompiler/backend/glasm/emit_context.h" | ||
| 8 | #include "shader_recompiler/backend/glasm/emit_glasm_instructions.h" | ||
| 9 | #include "shader_recompiler/frontend/ir/modifiers.h" | ||
| 10 | #include "shader_recompiler/frontend/ir/value.h" | ||
| 11 | |||
| 12 | namespace Shader::Backend::GLASM { | ||
| 13 | namespace { | ||
| 14 | std::string_view FpRounding(IR::FpRounding fp_rounding) { | ||
| 15 | switch (fp_rounding) { | ||
| 16 | case IR::FpRounding::DontCare: | ||
| 17 | return ""; | ||
| 18 | case IR::FpRounding::RN: | ||
| 19 | return ".ROUND"; | ||
| 20 | case IR::FpRounding::RZ: | ||
| 21 | return ".TRUNC"; | ||
| 22 | case IR::FpRounding::RM: | ||
| 23 | return ".FLR"; | ||
| 24 | case IR::FpRounding::RP: | ||
| 25 | return ".CEIL"; | ||
| 26 | } | ||
| 27 | throw InvalidArgument("Invalid floating-point rounding {}", fp_rounding); | ||
| 28 | } | ||
| 29 | |||
| 30 | template <typename InputType> | ||
| 31 | void Convert(EmitContext& ctx, IR::Inst& inst, InputType value, std::string_view dest, | ||
| 32 | std::string_view src, bool is_long_result) { | ||
| 33 | const std::string_view fp_rounding{FpRounding(inst.Flags<IR::FpControl>().rounding)}; | ||
| 34 | const auto ret{is_long_result ? ctx.reg_alloc.LongDefine(inst) : ctx.reg_alloc.Define(inst)}; | ||
| 35 | ctx.Add("CVT.{}.{}{} {}.x,{};", dest, src, fp_rounding, ret, value); | ||
| 36 | } | ||
| 37 | } // Anonymous namespace | ||
| 38 | |||
| 39 | void EmitConvertS16F16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 40 | Convert(ctx, inst, value, "S16", "F16", false); | ||
| 41 | } | ||
| 42 | |||
| 43 | void EmitConvertS16F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { | ||
| 44 | Convert(ctx, inst, value, "S16", "F32", false); | ||
| 45 | } | ||
| 46 | |||
| 47 | void EmitConvertS16F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { | ||
| 48 | Convert(ctx, inst, value, "S16", "F64", false); | ||
| 49 | } | ||
| 50 | |||
| 51 | void EmitConvertS32F16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 52 | Convert(ctx, inst, value, "S32", "F16", false); | ||
| 53 | } | ||
| 54 | |||
| 55 | void EmitConvertS32F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { | ||
| 56 | Convert(ctx, inst, value, "S32", "F32", false); | ||
| 57 | } | ||
| 58 | |||
| 59 | void EmitConvertS32F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { | ||
| 60 | Convert(ctx, inst, value, "S32", "F64", false); | ||
| 61 | } | ||
| 62 | |||
| 63 | void EmitConvertS64F16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 64 | Convert(ctx, inst, value, "S64", "F16", true); | ||
| 65 | } | ||
| 66 | |||
| 67 | void EmitConvertS64F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { | ||
| 68 | Convert(ctx, inst, value, "S64", "F32", true); | ||
| 69 | } | ||
| 70 | |||
| 71 | void EmitConvertS64F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { | ||
| 72 | Convert(ctx, inst, value, "S64", "F64", true); | ||
| 73 | } | ||
| 74 | |||
| 75 | void EmitConvertU16F16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 76 | Convert(ctx, inst, value, "U16", "F16", false); | ||
| 77 | } | ||
| 78 | |||
| 79 | void EmitConvertU16F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { | ||
| 80 | Convert(ctx, inst, value, "U16", "F32", false); | ||
| 81 | } | ||
| 82 | |||
| 83 | void EmitConvertU16F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { | ||
| 84 | Convert(ctx, inst, value, "U16", "F64", false); | ||
| 85 | } | ||
| 86 | |||
| 87 | void EmitConvertU32F16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 88 | Convert(ctx, inst, value, "U32", "F16", false); | ||
| 89 | } | ||
| 90 | |||
| 91 | void EmitConvertU32F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { | ||
| 92 | Convert(ctx, inst, value, "U32", "F32", false); | ||
| 93 | } | ||
| 94 | |||
| 95 | void EmitConvertU32F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { | ||
| 96 | Convert(ctx, inst, value, "U32", "F64", false); | ||
| 97 | } | ||
| 98 | |||
| 99 | void EmitConvertU64F16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 100 | Convert(ctx, inst, value, "U64", "F16", true); | ||
| 101 | } | ||
| 102 | |||
| 103 | void EmitConvertU64F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { | ||
| 104 | Convert(ctx, inst, value, "U64", "F32", true); | ||
| 105 | } | ||
| 106 | |||
| 107 | void EmitConvertU64F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { | ||
| 108 | Convert(ctx, inst, value, "U64", "F64", true); | ||
| 109 | } | ||
| 110 | |||
| 111 | void EmitConvertU64U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value) { | ||
| 112 | Convert(ctx, inst, value, "U64", "U32", true); | ||
| 113 | } | ||
| 114 | |||
| 115 | void EmitConvertU32U64(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 116 | Convert(ctx, inst, value, "U32", "U64", false); | ||
| 117 | } | ||
| 118 | |||
| 119 | void EmitConvertF16F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { | ||
| 120 | Convert(ctx, inst, value, "F16", "F32", false); | ||
| 121 | } | ||
| 122 | |||
| 123 | void EmitConvertF32F16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 124 | Convert(ctx, inst, value, "F32", "F16", false); | ||
| 125 | } | ||
| 126 | |||
| 127 | void EmitConvertF32F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { | ||
| 128 | Convert(ctx, inst, value, "F32", "F64", false); | ||
| 129 | } | ||
| 130 | |||
| 131 | void EmitConvertF64F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { | ||
| 132 | Convert(ctx, inst, value, "F64", "F32", true); | ||
| 133 | } | ||
| 134 | |||
| 135 | void EmitConvertF16S8(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 136 | Convert(ctx, inst, value, "F16", "S8", false); | ||
| 137 | } | ||
| 138 | |||
| 139 | void EmitConvertF16S16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 140 | Convert(ctx, inst, value, "F16", "S16", false); | ||
| 141 | } | ||
| 142 | |||
| 143 | void EmitConvertF16S32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) { | ||
| 144 | Convert(ctx, inst, value, "F16", "S32", false); | ||
| 145 | } | ||
| 146 | |||
| 147 | void EmitConvertF16S64(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 148 | Convert(ctx, inst, value, "F16", "S64", false); | ||
| 149 | } | ||
| 150 | |||
| 151 | void EmitConvertF16U8(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 152 | Convert(ctx, inst, value, "F16", "U8", false); | ||
| 153 | } | ||
| 154 | |||
| 155 | void EmitConvertF16U16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 156 | Convert(ctx, inst, value, "F16", "U16", false); | ||
| 157 | } | ||
| 158 | |||
| 159 | void EmitConvertF16U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value) { | ||
| 160 | Convert(ctx, inst, value, "F16", "U32", false); | ||
| 161 | } | ||
| 162 | |||
| 163 | void EmitConvertF16U64(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 164 | Convert(ctx, inst, value, "F16", "U64", false); | ||
| 165 | } | ||
| 166 | |||
| 167 | void EmitConvertF32S8(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 168 | Convert(ctx, inst, value, "F32", "S8", false); | ||
| 169 | } | ||
| 170 | |||
| 171 | void EmitConvertF32S16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 172 | Convert(ctx, inst, value, "F32", "S16", false); | ||
| 173 | } | ||
| 174 | |||
| 175 | void EmitConvertF32S32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) { | ||
| 176 | Convert(ctx, inst, value, "F32", "S32", false); | ||
| 177 | } | ||
| 178 | |||
| 179 | void EmitConvertF32S64(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 180 | Convert(ctx, inst, value, "F32", "S64", false); | ||
| 181 | } | ||
| 182 | |||
| 183 | void EmitConvertF32U8(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 184 | Convert(ctx, inst, value, "F32", "U8", false); | ||
| 185 | } | ||
| 186 | |||
| 187 | void EmitConvertF32U16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 188 | Convert(ctx, inst, value, "F32", "U16", false); | ||
| 189 | } | ||
| 190 | |||
| 191 | void EmitConvertF32U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value) { | ||
| 192 | Convert(ctx, inst, value, "F32", "U32", false); | ||
| 193 | } | ||
| 194 | |||
| 195 | void EmitConvertF32U64(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 196 | Convert(ctx, inst, value, "F32", "U64", false); | ||
| 197 | } | ||
| 198 | |||
| 199 | void EmitConvertF64S8(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 200 | Convert(ctx, inst, value, "F64", "S8", true); | ||
| 201 | } | ||
| 202 | |||
| 203 | void EmitConvertF64S16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 204 | Convert(ctx, inst, value, "F64", "S16", true); | ||
| 205 | } | ||
| 206 | |||
| 207 | void EmitConvertF64S32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) { | ||
| 208 | Convert(ctx, inst, value, "F64", "S32", true); | ||
| 209 | } | ||
| 210 | |||
| 211 | void EmitConvertF64S64(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 212 | Convert(ctx, inst, value, "F64", "S64", true); | ||
| 213 | } | ||
| 214 | |||
| 215 | void EmitConvertF64U8(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 216 | Convert(ctx, inst, value, "F64", "U8", true); | ||
| 217 | } | ||
| 218 | |||
| 219 | void EmitConvertF64U16(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 220 | Convert(ctx, inst, value, "F64", "U16", true); | ||
| 221 | } | ||
| 222 | |||
| 223 | void EmitConvertF64U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value) { | ||
| 224 | Convert(ctx, inst, value, "F64", "U32", true); | ||
| 225 | } | ||
| 226 | |||
| 227 | void EmitConvertF64U64(EmitContext& ctx, IR::Inst& inst, Register value) { | ||
| 228 | Convert(ctx, inst, value, "F64", "U64", true); | ||
| 229 | } | ||
| 230 | |||
| 231 | } // namespace Shader::Backend::GLASM | ||
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_floating_point.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_floating_point.cpp index aab506109..2aee5a56c 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_floating_point.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm_floating_point.cpp | |||
| @@ -169,62 +169,68 @@ void EmitFPClamp16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register | |||
| 169 | throw NotImplementedException("GLASM instruction"); | 169 | throw NotImplementedException("GLASM instruction"); |
| 170 | } | 170 | } |
| 171 | 171 | ||
| 172 | void EmitFPClamp32([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] ScalarF32 value, | 172 | void EmitFPClamp32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value, ScalarF32 min_value, |
| 173 | [[maybe_unused]] ScalarF32 min_value, [[maybe_unused]] ScalarF32 max_value) { | 173 | ScalarF32 max_value) { |
| 174 | throw NotImplementedException("GLASM instruction"); | 174 | const Register ret{ctx.reg_alloc.Define(inst)}; |
| 175 | ctx.Add("MIN.F {}.x,{},{};" | ||
| 176 | "MAX.F {}.x,{},{};", | ||
| 177 | ret, max_value, value, ret, ret, min_value); | ||
| 175 | } | 178 | } |
| 176 | 179 | ||
| 177 | void EmitFPClamp64([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value, | 180 | void EmitFPClamp64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value, ScalarF64 min_value, |
| 178 | [[maybe_unused]] Register min_value, [[maybe_unused]] Register max_value) { | 181 | ScalarF64 max_value) { |
| 179 | throw NotImplementedException("GLASM instruction"); | 182 | const Register ret{ctx.reg_alloc.LongDefine(inst)}; |
| 183 | ctx.Add("MIN.F64 {}.x,{},{};" | ||
| 184 | "MAX.F64 {}.x,{},{};", | ||
| 185 | ret, max_value, value, ret, ret, min_value); | ||
| 180 | } | 186 | } |
| 181 | 187 | ||
| 182 | void EmitFPRoundEven16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 188 | void EmitFPRoundEven16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { |
| 183 | throw NotImplementedException("GLASM instruction"); | 189 | throw NotImplementedException("GLASM instruction"); |
| 184 | } | 190 | } |
| 185 | 191 | ||
| 186 | void EmitFPRoundEven32([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] ScalarF32 value) { | 192 | void EmitFPRoundEven32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { |
| 187 | throw NotImplementedException("GLASM instruction"); | 193 | ctx.Add("ROUND.F {}.x,{};", inst, value); |
| 188 | } | 194 | } |
| 189 | 195 | ||
| 190 | void EmitFPRoundEven64([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 196 | void EmitFPRoundEven64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { |
| 191 | throw NotImplementedException("GLASM instruction"); | 197 | ctx.LongAdd("ROUND.F64 {}.x,{};", inst, value); |
| 192 | } | 198 | } |
| 193 | 199 | ||
| 194 | void EmitFPFloor16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 200 | void EmitFPFloor16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { |
| 195 | throw NotImplementedException("GLASM instruction"); | 201 | throw NotImplementedException("GLASM instruction"); |
| 196 | } | 202 | } |
| 197 | 203 | ||
| 198 | void EmitFPFloor32([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] ScalarF32 value) { | 204 | void EmitFPFloor32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { |
| 199 | throw NotImplementedException("GLASM instruction"); | 205 | ctx.Add("FLR.F {}.x,{};", inst, value); |
| 200 | } | 206 | } |
| 201 | 207 | ||
| 202 | void EmitFPFloor64([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 208 | void EmitFPFloor64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { |
| 203 | throw NotImplementedException("GLASM instruction"); | 209 | ctx.LongAdd("FLR.F64 {}.x,{};", inst, value); |
| 204 | } | 210 | } |
| 205 | 211 | ||
| 206 | void EmitFPCeil16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 212 | void EmitFPCeil16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { |
| 207 | throw NotImplementedException("GLASM instruction"); | 213 | throw NotImplementedException("GLASM instruction"); |
| 208 | } | 214 | } |
| 209 | 215 | ||
| 210 | void EmitFPCeil32([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] ScalarF32 value) { | 216 | void EmitFPCeil32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { |
| 211 | throw NotImplementedException("GLASM instruction"); | 217 | ctx.Add("CEIL.F {}.x,{};", inst, value); |
| 212 | } | 218 | } |
| 213 | 219 | ||
| 214 | void EmitFPCeil64([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 220 | void EmitFPCeil64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { |
| 215 | throw NotImplementedException("GLASM instruction"); | 221 | ctx.LongAdd("CEIL.F64 {}.x,{};", inst, value); |
| 216 | } | 222 | } |
| 217 | 223 | ||
| 218 | void EmitFPTrunc16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 224 | void EmitFPTrunc16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { |
| 219 | throw NotImplementedException("GLASM instruction"); | 225 | throw NotImplementedException("GLASM instruction"); |
| 220 | } | 226 | } |
| 221 | 227 | ||
| 222 | void EmitFPTrunc32([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] ScalarF32 value) { | 228 | void EmitFPTrunc32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value) { |
| 223 | throw NotImplementedException("GLASM instruction"); | 229 | ctx.Add("TRUNC.F {}.x,{};", inst, value); |
| 224 | } | 230 | } |
| 225 | 231 | ||
| 226 | void EmitFPTrunc64([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register value) { | 232 | void EmitFPTrunc64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value) { |
| 227 | throw NotImplementedException("GLASM instruction"); | 233 | ctx.LongAdd("TRUNC.F64 {}.x,{};", inst, value); |
| 228 | } | 234 | } |
| 229 | 235 | ||
| 230 | void EmitFPOrdEqual16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register lhs, | 236 | void EmitFPOrdEqual16([[maybe_unused]] EmitContext& ctx, [[maybe_unused]] Register lhs, |
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h b/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h index 5d94f21a6..94843cc60 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h +++ b/src/shader_recompiler/backend/glasm/emit_glasm_instructions.h | |||
| @@ -198,8 +198,8 @@ void EmitBitCastU64F64(EmitContext& ctx, IR::Inst& inst, const IR::Value& value) | |||
| 198 | void EmitBitCastF16U16(EmitContext& ctx, IR::Inst& inst, const IR::Value& value); | 198 | void EmitBitCastF16U16(EmitContext& ctx, IR::Inst& inst, const IR::Value& value); |
| 199 | void EmitBitCastF32U32(EmitContext& ctx, IR::Inst& inst, const IR::Value& value); | 199 | void EmitBitCastF32U32(EmitContext& ctx, IR::Inst& inst, const IR::Value& value); |
| 200 | void EmitBitCastF64U64(EmitContext& ctx, IR::Inst& inst, const IR::Value& value); | 200 | void EmitBitCastF64U64(EmitContext& ctx, IR::Inst& inst, const IR::Value& value); |
| 201 | void EmitPackUint2x32(EmitContext& ctx, Register value); | 201 | void EmitPackUint2x32(EmitContext& ctx, IR::Inst& inst, Register value); |
| 202 | void EmitUnpackUint2x32(EmitContext& ctx, Register value); | 202 | void EmitUnpackUint2x32(EmitContext& ctx, IR::Inst& inst, Register value); |
| 203 | void EmitPackFloat2x16(EmitContext& ctx, Register value); | 203 | void EmitPackFloat2x16(EmitContext& ctx, Register value); |
| 204 | void EmitUnpackFloat2x16(EmitContext& ctx, Register value); | 204 | void EmitUnpackFloat2x16(EmitContext& ctx, Register value); |
| 205 | void EmitPackHalf2x16(EmitContext& ctx, IR::Inst& inst, Register value); | 205 | void EmitPackHalf2x16(EmitContext& ctx, IR::Inst& inst, Register value); |
| @@ -244,20 +244,22 @@ void EmitFPSaturate16(EmitContext& ctx, Register value); | |||
| 244 | void EmitFPSaturate32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); | 244 | void EmitFPSaturate32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 245 | void EmitFPSaturate64(EmitContext& ctx, Register value); | 245 | void EmitFPSaturate64(EmitContext& ctx, Register value); |
| 246 | void EmitFPClamp16(EmitContext& ctx, Register value, Register min_value, Register max_value); | 246 | void EmitFPClamp16(EmitContext& ctx, Register value, Register min_value, Register max_value); |
| 247 | void EmitFPClamp32(EmitContext& ctx, ScalarF32 value, ScalarF32 min_value, ScalarF32 max_value); | 247 | void EmitFPClamp32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value, ScalarF32 min_value, |
| 248 | void EmitFPClamp64(EmitContext& ctx, Register value, Register min_value, Register max_value); | 248 | ScalarF32 max_value); |
| 249 | void EmitFPClamp64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value, ScalarF64 min_value, | ||
| 250 | ScalarF64 max_value); | ||
| 249 | void EmitFPRoundEven16(EmitContext& ctx, Register value); | 251 | void EmitFPRoundEven16(EmitContext& ctx, Register value); |
| 250 | void EmitFPRoundEven32(EmitContext& ctx, ScalarF32 value); | 252 | void EmitFPRoundEven32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 251 | void EmitFPRoundEven64(EmitContext& ctx, Register value); | 253 | void EmitFPRoundEven64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 252 | void EmitFPFloor16(EmitContext& ctx, Register value); | 254 | void EmitFPFloor16(EmitContext& ctx, Register value); |
| 253 | void EmitFPFloor32(EmitContext& ctx, ScalarF32 value); | 255 | void EmitFPFloor32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 254 | void EmitFPFloor64(EmitContext& ctx, Register value); | 256 | void EmitFPFloor64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 255 | void EmitFPCeil16(EmitContext& ctx, Register value); | 257 | void EmitFPCeil16(EmitContext& ctx, Register value); |
| 256 | void EmitFPCeil32(EmitContext& ctx, ScalarF32 value); | 258 | void EmitFPCeil32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 257 | void EmitFPCeil64(EmitContext& ctx, Register value); | 259 | void EmitFPCeil64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 258 | void EmitFPTrunc16(EmitContext& ctx, Register value); | 260 | void EmitFPTrunc16(EmitContext& ctx, Register value); |
| 259 | void EmitFPTrunc32(EmitContext& ctx, ScalarF32 value); | 261 | void EmitFPTrunc32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 260 | void EmitFPTrunc64(EmitContext& ctx, Register value); | 262 | void EmitFPTrunc64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 261 | void EmitFPOrdEqual16(EmitContext& ctx, Register lhs, Register rhs); | 263 | void EmitFPOrdEqual16(EmitContext& ctx, Register lhs, Register rhs); |
| 262 | void EmitFPOrdEqual32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs); | 264 | void EmitFPOrdEqual32(EmitContext& ctx, IR::Inst& inst, ScalarF32 lhs, ScalarF32 rhs); |
| 263 | void EmitFPOrdEqual64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs); | 265 | void EmitFPOrdEqual64(EmitContext& ctx, IR::Inst& inst, ScalarF64 lhs, ScalarF64 rhs); |
| @@ -441,54 +443,54 @@ void EmitLogicalOr(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); | |||
| 441 | void EmitLogicalAnd(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); | 443 | void EmitLogicalAnd(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); |
| 442 | void EmitLogicalXor(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); | 444 | void EmitLogicalXor(EmitContext& ctx, IR::Inst& inst, ScalarS32 a, ScalarS32 b); |
| 443 | void EmitLogicalNot(EmitContext& ctx, IR::Inst& inst, ScalarS32 value); | 445 | void EmitLogicalNot(EmitContext& ctx, IR::Inst& inst, ScalarS32 value); |
| 444 | void EmitConvertS16F16(EmitContext& ctx, Register value); | 446 | void EmitConvertS16F16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 445 | void EmitConvertS16F32(EmitContext& ctx, Register value); | 447 | void EmitConvertS16F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 446 | void EmitConvertS16F64(EmitContext& ctx, Register value); | 448 | void EmitConvertS16F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 447 | void EmitConvertS32F16(EmitContext& ctx, Register value); | 449 | void EmitConvertS32F16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 448 | void EmitConvertS32F32(EmitContext& ctx, Register value); | 450 | void EmitConvertS32F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 449 | void EmitConvertS32F64(EmitContext& ctx, Register value); | 451 | void EmitConvertS32F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 450 | void EmitConvertS64F16(EmitContext& ctx, Register value); | 452 | void EmitConvertS64F16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 451 | void EmitConvertS64F32(EmitContext& ctx, Register value); | 453 | void EmitConvertS64F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 452 | void EmitConvertS64F64(EmitContext& ctx, Register value); | 454 | void EmitConvertS64F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 453 | void EmitConvertU16F16(EmitContext& ctx, Register value); | 455 | void EmitConvertU16F16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 454 | void EmitConvertU16F32(EmitContext& ctx, Register value); | 456 | void EmitConvertU16F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 455 | void EmitConvertU16F64(EmitContext& ctx, Register value); | 457 | void EmitConvertU16F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 456 | void EmitConvertU32F16(EmitContext& ctx, Register value); | 458 | void EmitConvertU32F16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 457 | void EmitConvertU32F32(EmitContext& ctx, Register value); | 459 | void EmitConvertU32F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 458 | void EmitConvertU32F64(EmitContext& ctx, Register value); | 460 | void EmitConvertU32F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 459 | void EmitConvertU64F16(EmitContext& ctx, Register value); | 461 | void EmitConvertU64F16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 460 | void EmitConvertU64F32(EmitContext& ctx, Register value); | 462 | void EmitConvertU64F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 461 | void EmitConvertU64F64(EmitContext& ctx, Register value); | 463 | void EmitConvertU64F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 462 | void EmitConvertU64U32(EmitContext& ctx, Register value); | 464 | void EmitConvertU64U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value); |
| 463 | void EmitConvertU32U64(EmitContext& ctx, Register value); | 465 | void EmitConvertU32U64(EmitContext& ctx, IR::Inst& inst, Register value); |
| 464 | void EmitConvertF16F32(EmitContext& ctx, Register value); | 466 | void EmitConvertF16F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 465 | void EmitConvertF32F16(EmitContext& ctx, Register value); | 467 | void EmitConvertF32F16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 466 | void EmitConvertF32F64(EmitContext& ctx, Register value); | 468 | void EmitConvertF32F64(EmitContext& ctx, IR::Inst& inst, ScalarF64 value); |
| 467 | void EmitConvertF64F32(EmitContext& ctx, Register value); | 469 | void EmitConvertF64F32(EmitContext& ctx, IR::Inst& inst, ScalarF32 value); |
| 468 | void EmitConvertF16S8(EmitContext& ctx, Register value); | 470 | void EmitConvertF16S8(EmitContext& ctx, IR::Inst& inst, Register value); |
| 469 | void EmitConvertF16S16(EmitContext& ctx, Register value); | 471 | void EmitConvertF16S16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 470 | void EmitConvertF16S32(EmitContext& ctx, Register value); | 472 | void EmitConvertF16S32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value); |
| 471 | void EmitConvertF16S64(EmitContext& ctx, Register value); | 473 | void EmitConvertF16S64(EmitContext& ctx, IR::Inst& inst, Register value); |
| 472 | void EmitConvertF16U8(EmitContext& ctx, Register value); | 474 | void EmitConvertF16U8(EmitContext& ctx, IR::Inst& inst, Register value); |
| 473 | void EmitConvertF16U16(EmitContext& ctx, Register value); | 475 | void EmitConvertF16U16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 474 | void EmitConvertF16U32(EmitContext& ctx, Register value); | 476 | void EmitConvertF16U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value); |
| 475 | void EmitConvertF16U64(EmitContext& ctx, Register value); | 477 | void EmitConvertF16U64(EmitContext& ctx, IR::Inst& inst, Register value); |
| 476 | void EmitConvertF32S8(EmitContext& ctx, Register value); | 478 | void EmitConvertF32S8(EmitContext& ctx, IR::Inst& inst, Register value); |
| 477 | void EmitConvertF32S16(EmitContext& ctx, Register value); | 479 | void EmitConvertF32S16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 478 | void EmitConvertF32S32(EmitContext& ctx, Register value); | 480 | void EmitConvertF32S32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value); |
| 479 | void EmitConvertF32S64(EmitContext& ctx, Register value); | 481 | void EmitConvertF32S64(EmitContext& ctx, IR::Inst& inst, Register value); |
| 480 | void EmitConvertF32U8(EmitContext& ctx, Register value); | 482 | void EmitConvertF32U8(EmitContext& ctx, IR::Inst& inst, Register value); |
| 481 | void EmitConvertF32U16(EmitContext& ctx, Register value); | 483 | void EmitConvertF32U16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 482 | void EmitConvertF32U32(EmitContext& ctx, Register value); | 484 | void EmitConvertF32U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value); |
| 483 | void EmitConvertF32U64(EmitContext& ctx, Register value); | 485 | void EmitConvertF32U64(EmitContext& ctx, IR::Inst& inst, Register value); |
| 484 | void EmitConvertF64S8(EmitContext& ctx, Register value); | 486 | void EmitConvertF64S8(EmitContext& ctx, IR::Inst& inst, Register value); |
| 485 | void EmitConvertF64S16(EmitContext& ctx, Register value); | 487 | void EmitConvertF64S16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 486 | void EmitConvertF64S32(EmitContext& ctx, Register value); | 488 | void EmitConvertF64S32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value); |
| 487 | void EmitConvertF64S64(EmitContext& ctx, Register value); | 489 | void EmitConvertF64S64(EmitContext& ctx, IR::Inst& inst, Register value); |
| 488 | void EmitConvertF64U8(EmitContext& ctx, Register value); | 490 | void EmitConvertF64U8(EmitContext& ctx, IR::Inst& inst, Register value); |
| 489 | void EmitConvertF64U16(EmitContext& ctx, Register value); | 491 | void EmitConvertF64U16(EmitContext& ctx, IR::Inst& inst, Register value); |
| 490 | void EmitConvertF64U32(EmitContext& ctx, Register value); | 492 | void EmitConvertF64U32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value); |
| 491 | void EmitConvertF64U64(EmitContext& ctx, Register value); | 493 | void EmitConvertF64U64(EmitContext& ctx, IR::Inst& inst, Register value); |
| 492 | void EmitBindlessImageSampleImplicitLod(EmitContext&); | 494 | void EmitBindlessImageSampleImplicitLod(EmitContext&); |
| 493 | void EmitBindlessImageSampleExplicitLod(EmitContext&); | 495 | void EmitBindlessImageSampleExplicitLod(EmitContext&); |
| 494 | void EmitBindlessImageSampleDrefImplicitLod(EmitContext&); | 496 | void EmitBindlessImageSampleDrefImplicitLod(EmitContext&); |
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp index c9386805a..40f48a091 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm_integer.cpp | |||
| @@ -141,14 +141,16 @@ void EmitUMax32(EmitContext& ctx, IR::Inst& inst, ScalarU32 a, ScalarU32 b) { | |||
| 141 | 141 | ||
| 142 | void EmitSClamp32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value, ScalarS32 min, ScalarS32 max) { | 142 | void EmitSClamp32(EmitContext& ctx, IR::Inst& inst, ScalarS32 value, ScalarS32 min, ScalarS32 max) { |
| 143 | const Register ret{ctx.reg_alloc.Define(inst)}; | 143 | const Register ret{ctx.reg_alloc.Define(inst)}; |
| 144 | ctx.Add("MIN.S {}.x,{},{};", ret, max, value); | 144 | ctx.Add("MIN.S {}.x,{},{};" |
| 145 | ctx.Add("MAX.S {}.x,{},{};", ret, ret, min); | 145 | "MAX.S {}.x,{},{};", |
| 146 | ret, max, value, ret, ret, min); | ||
| 146 | } | 147 | } |
| 147 | 148 | ||
| 148 | void EmitUClamp32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 min, ScalarU32 max) { | 149 | void EmitUClamp32(EmitContext& ctx, IR::Inst& inst, ScalarU32 value, ScalarU32 min, ScalarU32 max) { |
| 149 | const Register ret{ctx.reg_alloc.Define(inst)}; | 150 | const Register ret{ctx.reg_alloc.Define(inst)}; |
| 150 | ctx.Add("MIN.U {}.x,{},{};", ret, max, value); | 151 | ctx.Add("MIN.U {}.x,{},{};" |
| 151 | ctx.Add("MAX.U {}.x,{},{};", ret, ret, min); | 152 | "MAX.U {}.x,{},{};", |
| 153 | ret, max, value, ret, ret, min); | ||
| 152 | } | 154 | } |
| 153 | 155 | ||
| 154 | void EmitSLessThan(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs) { | 156 | void EmitSLessThan(EmitContext& ctx, IR::Inst& inst, ScalarS32 lhs, ScalarS32 rhs) { |
diff --git a/src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp b/src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp index 29eb75c6a..ebdbbcf5f 100644 --- a/src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp +++ b/src/shader_recompiler/backend/glasm/emit_glasm_not_implemented.cpp | |||
| @@ -588,198 +588,6 @@ void EmitLogicalNot(EmitContext& ctx, IR::Inst& inst, ScalarS32 value) { | |||
| 588 | ctx.Add("SEQ.S {},{},0;", inst, value); | 588 | ctx.Add("SEQ.S {},{},0;", inst, value); |
| 589 | } | 589 | } |
| 590 | 590 | ||
| 591 | void EmitConvertS16F16(EmitContext& ctx, Register value) { | ||
| 592 | NotImplemented(); | ||
| 593 | } | ||
| 594 | |||
| 595 | void EmitConvertS16F32(EmitContext& ctx, Register value) { | ||
| 596 | NotImplemented(); | ||
| 597 | } | ||
| 598 | |||
| 599 | void EmitConvertS16F64(EmitContext& ctx, Register value) { | ||
| 600 | NotImplemented(); | ||
| 601 | } | ||
| 602 | |||
| 603 | void EmitConvertS32F16(EmitContext& ctx, Register value) { | ||
| 604 | NotImplemented(); | ||
| 605 | } | ||
| 606 | |||
| 607 | void EmitConvertS32F32(EmitContext& ctx, Register value) { | ||
| 608 | NotImplemented(); | ||
| 609 | } | ||
| 610 | |||
| 611 | void EmitConvertS32F64(EmitContext& ctx, Register value) { | ||
| 612 | NotImplemented(); | ||
| 613 | } | ||
| 614 | |||
| 615 | void EmitConvertS64F16(EmitContext& ctx, Register value) { | ||
| 616 | NotImplemented(); | ||
| 617 | } | ||
| 618 | |||
| 619 | void EmitConvertS64F32(EmitContext& ctx, Register value) { | ||
| 620 | NotImplemented(); | ||
| 621 | } | ||
| 622 | |||
| 623 | void EmitConvertS64F64(EmitContext& ctx, Register value) { | ||
| 624 | NotImplemented(); | ||
| 625 | } | ||
| 626 | |||
| 627 | void EmitConvertU16F16(EmitContext& ctx, Register value) { | ||
| 628 | NotImplemented(); | ||
| 629 | } | ||
| 630 | |||
| 631 | void EmitConvertU16F32(EmitContext& ctx, Register value) { | ||
| 632 | NotImplemented(); | ||
| 633 | } | ||
| 634 | |||
| 635 | void EmitConvertU16F64(EmitContext& ctx, Register value) { | ||
| 636 | NotImplemented(); | ||
| 637 | } | ||
| 638 | |||
| 639 | void EmitConvertU32F16(EmitContext& ctx, Register value) { | ||
| 640 | NotImplemented(); | ||
| 641 | } | ||
| 642 | |||
| 643 | void EmitConvertU32F32(EmitContext& ctx, Register value) { | ||
| 644 | NotImplemented(); | ||
| 645 | } | ||
| 646 | |||
| 647 | void EmitConvertU32F64(EmitContext& ctx, Register value) { | ||
| 648 | NotImplemented(); | ||
| 649 | } | ||
| 650 | |||
| 651 | void EmitConvertU64F16(EmitContext& ctx, Register value) { | ||
| 652 | NotImplemented(); | ||
| 653 | } | ||
| 654 | |||
| 655 | void EmitConvertU64F32(EmitContext& ctx, Register value) { | ||
| 656 | NotImplemented(); | ||
| 657 | } | ||
| 658 | |||
| 659 | void EmitConvertU64F64(EmitContext& ctx, Register value) { | ||
| 660 | NotImplemented(); | ||
| 661 | } | ||
| 662 | |||
| 663 | void EmitConvertU64U32(EmitContext& ctx, Register value) { | ||
| 664 | NotImplemented(); | ||
| 665 | } | ||
| 666 | |||
| 667 | void EmitConvertU32U64(EmitContext& ctx, Register value) { | ||
| 668 | NotImplemented(); | ||
| 669 | } | ||
| 670 | |||
| 671 | void EmitConvertF16F32(EmitContext& ctx, Register value) { | ||
| 672 | NotImplemented(); | ||
| 673 | } | ||
| 674 | |||
| 675 | void EmitConvertF32F16(EmitContext& ctx, Register value) { | ||
| 676 | NotImplemented(); | ||
| 677 | } | ||
| 678 | |||
| 679 | void EmitConvertF32F64(EmitContext& ctx, Register value) { | ||
| 680 | NotImplemented(); | ||
| 681 | } | ||
| 682 | |||
| 683 | void EmitConvertF64F32(EmitContext& ctx, Register value) { | ||
| 684 | NotImplemented(); | ||
| 685 | } | ||
| 686 | |||
| 687 | void EmitConvertF16S8(EmitContext& ctx, Register value) { | ||
| 688 | NotImplemented(); | ||
| 689 | } | ||
| 690 | |||
| 691 | void EmitConvertF16S16(EmitContext& ctx, Register value) { | ||
| 692 | NotImplemented(); | ||
| 693 | } | ||
| 694 | |||
| 695 | void EmitConvertF16S32(EmitContext& ctx, Register value) { | ||
| 696 | NotImplemented(); | ||
| 697 | } | ||
| 698 | |||
| 699 | void EmitConvertF16S64(EmitContext& ctx, Register value) { | ||
| 700 | NotImplemented(); | ||
| 701 | } | ||
| 702 | |||
| 703 | void EmitConvertF16U8(EmitContext& ctx, Register value) { | ||
| 704 | NotImplemented(); | ||
| 705 | } | ||
| 706 | |||
| 707 | void EmitConvertF16U16(EmitContext& ctx, Register value) { | ||
| 708 | NotImplemented(); | ||
| 709 | } | ||
| 710 | |||
| 711 | void EmitConvertF16U32(EmitContext& ctx, Register value) { | ||
| 712 | NotImplemented(); | ||
| 713 | } | ||
| 714 | |||
| 715 | void EmitConvertF16U64(EmitContext& ctx, Register value) { | ||
| 716 | NotImplemented(); | ||
| 717 | } | ||
| 718 | |||
| 719 | void EmitConvertF32S8(EmitContext& ctx, Register value) { | ||
| 720 | NotImplemented(); | ||
| 721 | } | ||
| 722 | |||
| 723 | void EmitConvertF32S16(EmitContext& ctx, Register value) { | ||
| 724 | NotImplemented(); | ||
| 725 | } | ||
| 726 | |||
| 727 | void EmitConvertF32S32(EmitContext& ctx, Register value) { | ||
| 728 | NotImplemented(); | ||
| 729 | } | ||
| 730 | |||
| 731 | void EmitConvertF32S64(EmitContext& ctx, Register value) { | ||
| 732 | NotImplemented(); | ||
| 733 | } | ||
| 734 | |||
| 735 | void EmitConvertF32U8(EmitContext& ctx, Register value) { | ||
| 736 | NotImplemented(); | ||
| 737 | } | ||
| 738 | |||
| 739 | void EmitConvertF32U16(EmitContext& ctx, Register value) { | ||
| 740 | NotImplemented(); | ||
| 741 | } | ||
| 742 | |||
| 743 | void EmitConvertF32U32(EmitContext& ctx, Register value) { | ||
| 744 | NotImplemented(); | ||
| 745 | } | ||
| 746 | |||
| 747 | void EmitConvertF32U64(EmitContext& ctx, Register value) { | ||
| 748 | NotImplemented(); | ||
| 749 | } | ||
| 750 | |||
| 751 | void EmitConvertF64S8(EmitContext& ctx, Register value) { | ||
| 752 | NotImplemented(); | ||
| 753 | } | ||
| 754 | |||
| 755 | void EmitConvertF64S16(EmitContext& ctx, Register value) { | ||
| 756 | NotImplemented(); | ||
| 757 | } | ||
| 758 | |||
| 759 | void EmitConvertF64S32(EmitContext& ctx, Register value) { | ||
| 760 | NotImplemented(); | ||
| 761 | } | ||
| 762 | |||
| 763 | void EmitConvertF64S64(EmitContext& ctx, Register value) { | ||
| 764 | NotImplemented(); | ||
| 765 | } | ||
| 766 | |||
| 767 | void EmitConvertF64U8(EmitContext& ctx, Register value) { | ||
| 768 | NotImplemented(); | ||
| 769 | } | ||
| 770 | |||
| 771 | void EmitConvertF64U16(EmitContext& ctx, Register value) { | ||
| 772 | NotImplemented(); | ||
| 773 | } | ||
| 774 | |||
| 775 | void EmitConvertF64U32(EmitContext& ctx, Register value) { | ||
| 776 | NotImplemented(); | ||
| 777 | } | ||
| 778 | |||
| 779 | void EmitConvertF64U64(EmitContext& ctx, Register value) { | ||
| 780 | NotImplemented(); | ||
| 781 | } | ||
| 782 | |||
| 783 | void EmitBindlessImageSampleImplicitLod(EmitContext&) { | 591 | void EmitBindlessImageSampleImplicitLod(EmitContext&) { |
| 784 | NotImplemented(); | 592 | NotImplemented(); |
| 785 | } | 593 | } |
diff --git a/src/shader_recompiler/backend/glasm/reg_alloc.cpp b/src/shader_recompiler/backend/glasm/reg_alloc.cpp index 82b627500..1a65a5e7d 100644 --- a/src/shader_recompiler/backend/glasm/reg_alloc.cpp +++ b/src/shader_recompiler/backend/glasm/reg_alloc.cpp | |||
| @@ -39,6 +39,10 @@ Value RegAlloc::Consume(const IR::Value& value) { | |||
| 39 | ret.type = Type::F32; | 39 | ret.type = Type::F32; |
| 40 | ret.imm_f32 = value.F32(); | 40 | ret.imm_f32 = value.F32(); |
| 41 | break; | 41 | break; |
| 42 | case IR::Type::U64: | ||
| 43 | ret.type = Type::U64; | ||
| 44 | ret.imm_u64 = value.U64(); | ||
| 45 | break; | ||
| 42 | case IR::Type::F64: | 46 | case IR::Type::F64: |
| 43 | ret.type = Type::F64; | 47 | ret.type = Type::F64; |
| 44 | ret.imm_f64 = value.F64(); | 48 | ret.imm_f64 = value.F64(); |
diff --git a/src/shader_recompiler/backend/glasm/reg_alloc.h b/src/shader_recompiler/backend/glasm/reg_alloc.h index f1899eae1..200c51610 100644 --- a/src/shader_recompiler/backend/glasm/reg_alloc.h +++ b/src/shader_recompiler/backend/glasm/reg_alloc.h | |||
| @@ -27,6 +27,7 @@ enum class Type : u32 { | |||
| 27 | U32, | 27 | U32, |
| 28 | S32, | 28 | S32, |
| 29 | F32, | 29 | F32, |
| 30 | U64, | ||
| 30 | F64, | 31 | F64, |
| 31 | }; | 32 | }; |
| 32 | 33 | ||
| @@ -55,6 +56,7 @@ struct Value { | |||
| 55 | u32 imm_u32; | 56 | u32 imm_u32; |
| 56 | s32 imm_s32; | 57 | s32 imm_s32; |
| 57 | f32 imm_f32; | 58 | f32 imm_f32; |
| 59 | u64 imm_u64; | ||
| 58 | f64 imm_f64; | 60 | f64 imm_f64; |
| 59 | }; | 61 | }; |
| 60 | 62 | ||
| @@ -71,6 +73,8 @@ struct Value { | |||
| 71 | return imm_s32 == rhs.imm_s32; | 73 | return imm_s32 == rhs.imm_s32; |
| 72 | case Type::F32: | 74 | case Type::F32: |
| 73 | return Common::BitCast<u32>(imm_f32) == Common::BitCast<u32>(rhs.imm_f32); | 75 | return Common::BitCast<u32>(imm_f32) == Common::BitCast<u32>(rhs.imm_f32); |
| 76 | case Type::U64: | ||
| 77 | return imm_u64 == rhs.imm_u64; | ||
| 74 | case Type::F64: | 78 | case Type::F64: |
| 75 | return Common::BitCast<u64>(imm_f64) == Common::BitCast<u64>(rhs.imm_f64); | 79 | return Common::BitCast<u64>(imm_f64) == Common::BitCast<u64>(rhs.imm_f64); |
| 76 | } | 80 | } |
| @@ -103,6 +107,10 @@ public: | |||
| 103 | 107 | ||
| 104 | void FreeReg(Register reg); | 108 | void FreeReg(Register reg); |
| 105 | 109 | ||
| 110 | void InvalidateConditionCodes() { | ||
| 111 | // This does nothing for now | ||
| 112 | } | ||
| 113 | |||
| 106 | [[nodiscard]] size_t NumUsedRegisters() const noexcept { | 114 | [[nodiscard]] size_t NumUsedRegisters() const noexcept { |
| 107 | return num_used_registers; | 115 | return num_used_registers; |
| 108 | } | 116 | } |
| @@ -210,6 +218,7 @@ struct fmt::formatter<Shader::Backend::GLASM::ScalarU32> { | |||
| 210 | return fmt::format_to(ctx.out(), "{}", static_cast<u32>(value.imm_s32)); | 218 | return fmt::format_to(ctx.out(), "{}", static_cast<u32>(value.imm_s32)); |
| 211 | case Shader::Backend::GLASM::Type::F32: | 219 | case Shader::Backend::GLASM::Type::F32: |
| 212 | return fmt::format_to(ctx.out(), "{}", Common::BitCast<u32>(value.imm_f32)); | 220 | return fmt::format_to(ctx.out(), "{}", Common::BitCast<u32>(value.imm_f32)); |
| 221 | case Shader::Backend::GLASM::Type::U64: | ||
| 213 | case Shader::Backend::GLASM::Type::F64: | 222 | case Shader::Backend::GLASM::Type::F64: |
| 214 | break; | 223 | break; |
| 215 | } | 224 | } |
| @@ -233,6 +242,7 @@ struct fmt::formatter<Shader::Backend::GLASM::ScalarS32> { | |||
| 233 | return fmt::format_to(ctx.out(), "{}", value.imm_s32); | 242 | return fmt::format_to(ctx.out(), "{}", value.imm_s32); |
| 234 | case Shader::Backend::GLASM::Type::F32: | 243 | case Shader::Backend::GLASM::Type::F32: |
| 235 | return fmt::format_to(ctx.out(), "{}", Common::BitCast<s32>(value.imm_f32)); | 244 | return fmt::format_to(ctx.out(), "{}", Common::BitCast<s32>(value.imm_f32)); |
| 245 | case Shader::Backend::GLASM::Type::U64: | ||
| 236 | case Shader::Backend::GLASM::Type::F64: | 246 | case Shader::Backend::GLASM::Type::F64: |
| 237 | break; | 247 | break; |
| 238 | } | 248 | } |
| @@ -256,6 +266,7 @@ struct fmt::formatter<Shader::Backend::GLASM::ScalarF32> { | |||
| 256 | return fmt::format_to(ctx.out(), "{}", Common::BitCast<s32>(value.imm_s32)); | 266 | return fmt::format_to(ctx.out(), "{}", Common::BitCast<s32>(value.imm_s32)); |
| 257 | case Shader::Backend::GLASM::Type::F32: | 267 | case Shader::Backend::GLASM::Type::F32: |
| 258 | return fmt::format_to(ctx.out(), "{}", value.imm_f32); | 268 | return fmt::format_to(ctx.out(), "{}", value.imm_f32); |
| 269 | case Shader::Backend::GLASM::Type::U64: | ||
| 259 | case Shader::Backend::GLASM::Type::F64: | 270 | case Shader::Backend::GLASM::Type::F64: |
| 260 | break; | 271 | break; |
| 261 | } | 272 | } |
| @@ -277,6 +288,8 @@ struct fmt::formatter<Shader::Backend::GLASM::ScalarF64> { | |||
| 277 | case Shader::Backend::GLASM::Type::S32: | 288 | case Shader::Backend::GLASM::Type::S32: |
| 278 | case Shader::Backend::GLASM::Type::F32: | 289 | case Shader::Backend::GLASM::Type::F32: |
| 279 | break; | 290 | break; |
| 291 | case Shader::Backend::GLASM::Type::U64: | ||
| 292 | return format_to(ctx.out(), "{}", Common::BitCast<f64>(value.imm_u64)); | ||
| 280 | case Shader::Backend::GLASM::Type::F64: | 293 | case Shader::Backend::GLASM::Type::F64: |
| 281 | return format_to(ctx.out(), "{}", value.imm_f64); | 294 | return format_to(ctx.out(), "{}", value.imm_f64); |
| 282 | } | 295 | } |