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authorGravatar ReinUsesLisp2021-02-08 02:54:35 -0300
committerGravatar ameerj2021-07-22 21:51:22 -0400
commit2930dccecc933d6748772e9f51a5724fe1e6771b (patch)
treeec4aa48062f8a2fcba31b1c64f769ddf25a87832 /src/shader_recompiler
parentshader: Better constant folding (diff)
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spirv: Initial SPIR-V support
Diffstat (limited to 'src/shader_recompiler')
-rw-r--r--src/shader_recompiler/CMakeLists.txt15
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.cpp134
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.h314
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp57
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp105
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp102
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp30
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp220
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp132
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp89
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_memory.cpp125
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_select.cpp25
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp29
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.cpp12
-rw-r--r--src/shader_recompiler/frontend/ir/opcodes.inc12
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/translate.cpp10
-rw-r--r--src/shader_recompiler/ir_opt/identity_removal_pass.cpp2
-rw-r--r--src/shader_recompiler/main.cpp21
18 files changed, 1400 insertions, 34 deletions
diff --git a/src/shader_recompiler/CMakeLists.txt b/src/shader_recompiler/CMakeLists.txt
index 248e90d4b..12fbcb37c 100644
--- a/src/shader_recompiler/CMakeLists.txt
+++ b/src/shader_recompiler/CMakeLists.txt
@@ -1,5 +1,16 @@
1add_executable(shader_recompiler 1add_executable(shader_recompiler
2 backend/spirv/emit_spirv.cpp
2 backend/spirv/emit_spirv.h 3 backend/spirv/emit_spirv.h
4 backend/spirv/emit_spirv_bitwise_conversion.cpp
5 backend/spirv/emit_spirv_composite.cpp
6 backend/spirv/emit_spirv_context_get_set.cpp
7 backend/spirv/emit_spirv_control_flow.cpp
8 backend/spirv/emit_spirv_floating_point.cpp
9 backend/spirv/emit_spirv_integer.cpp
10 backend/spirv/emit_spirv_logical.cpp
11 backend/spirv/emit_spirv_memory.cpp
12 backend/spirv/emit_spirv_select.cpp
13 backend/spirv/emit_spirv_undefined.cpp
3 environment.h 14 environment.h
4 exception.h 15 exception.h
5 file_environment.cpp 16 file_environment.cpp
@@ -72,7 +83,9 @@ add_executable(shader_recompiler
72 main.cpp 83 main.cpp
73 object_pool.h 84 object_pool.h
74) 85)
75target_link_libraries(shader_recompiler PRIVATE fmt::fmt) 86
87target_include_directories(video_core PRIVATE sirit)
88target_link_libraries(shader_recompiler PRIVATE fmt::fmt sirit)
76 89
77if (MSVC) 90if (MSVC)
78 target_compile_options(shader_recompiler PRIVATE 91 target_compile_options(shader_recompiler PRIVATE
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.cpp b/src/shader_recompiler/backend/spirv/emit_spirv.cpp
new file mode 100644
index 000000000..7c4269fad
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.cpp
@@ -0,0 +1,134 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include <numeric>
6#include <type_traits>
7
8#include "shader_recompiler/backend/spirv/emit_spirv.h"
9#include "shader_recompiler/frontend/ir/basic_block.h"
10#include "shader_recompiler/frontend/ir/function.h"
11#include "shader_recompiler/frontend/ir/microinstruction.h"
12#include "shader_recompiler/frontend/ir/program.h"
13
14namespace Shader::Backend::SPIRV {
15
16EmitContext::EmitContext(IR::Program& program) {
17 AddCapability(spv::Capability::Shader);
18 AddCapability(spv::Capability::Float16);
19 AddCapability(spv::Capability::Float64);
20 void_id = TypeVoid();
21
22 u1 = Name(TypeBool(), "u1");
23 f32.Define(*this, TypeFloat(32), "f32");
24 u32.Define(*this, TypeInt(32, false), "u32");
25 f16.Define(*this, TypeFloat(16), "f16");
26 f64.Define(*this, TypeFloat(64), "f64");
27
28 for (const IR::Function& function : program.functions) {
29 for (IR::Block* const block : function.blocks) {
30 block_label_map.emplace_back(block, OpLabel());
31 }
32 }
33 std::ranges::sort(block_label_map, {}, &std::pair<IR::Block*, Id>::first);
34}
35
36EmitContext::~EmitContext() = default;
37
38EmitSPIRV::EmitSPIRV(IR::Program& program) {
39 EmitContext ctx{program};
40 const Id void_function{ctx.TypeFunction(ctx.void_id)};
41 // FIXME: Forward declare functions (needs sirit support)
42 Id func{};
43 for (IR::Function& function : program.functions) {
44 func = ctx.OpFunction(ctx.void_id, spv::FunctionControlMask::MaskNone, void_function);
45 for (IR::Block* const block : function.blocks) {
46 ctx.AddLabel(ctx.BlockLabel(block));
47 for (IR::Inst& inst : block->Instructions()) {
48 EmitInst(ctx, &inst);
49 }
50 }
51 ctx.OpFunctionEnd();
52 }
53 ctx.AddEntryPoint(spv::ExecutionModel::GLCompute, func, "main");
54
55 std::vector<u32> result{ctx.Assemble()};
56 std::FILE* file{std::fopen("shader.spv", "wb")};
57 std::fwrite(result.data(), sizeof(u32), result.size(), file);
58 std::fclose(file);
59 std::system("spirv-dis shader.spv");
60 std::system("spirv-val shader.spv");
61}
62
63template <auto method>
64static void Invoke(EmitSPIRV& emit, EmitContext& ctx, IR::Inst* inst) {
65 using M = decltype(method);
66 using std::is_invocable_r_v;
67 if constexpr (is_invocable_r_v<Id, M, EmitSPIRV&, EmitContext&>) {
68 ctx.Define(inst, (emit.*method)(ctx));
69 } else if constexpr (is_invocable_r_v<Id, M, EmitSPIRV&, EmitContext&, Id>) {
70 ctx.Define(inst, (emit.*method)(ctx, ctx.Def(inst->Arg(0))));
71 } else if constexpr (is_invocable_r_v<Id, M, EmitSPIRV&, EmitContext&, Id, Id>) {
72 ctx.Define(inst, (emit.*method)(ctx, ctx.Def(inst->Arg(0)), ctx.Def(inst->Arg(1))));
73 } else if constexpr (is_invocable_r_v<Id, M, EmitSPIRV&, EmitContext&, Id, Id, Id>) {
74 ctx.Define(inst, (emit.*method)(ctx, ctx.Def(inst->Arg(0)), ctx.Def(inst->Arg(1)),
75 ctx.Def(inst->Arg(2))));
76 } else if constexpr (is_invocable_r_v<Id, M, EmitSPIRV&, EmitContext&, IR::Inst*, Id, Id>) {
77 ctx.Define(inst, (emit.*method)(ctx, inst, ctx.Def(inst->Arg(0)), ctx.Def(inst->Arg(1))));
78 } else if constexpr (is_invocable_r_v<Id, M, EmitSPIRV&, EmitContext&, IR::Inst*, Id, Id, Id>) {
79 ctx.Define(inst, (emit.*method)(ctx, inst, ctx.Def(inst->Arg(0)), ctx.Def(inst->Arg(1)),
80 ctx.Def(inst->Arg(2))));
81 } else if constexpr (is_invocable_r_v<Id, M, EmitSPIRV&, EmitContext&, Id, u32>) {
82 ctx.Define(inst, (emit.*method)(ctx, ctx.Def(inst->Arg(0)), inst->Arg(1).U32()));
83 } else if constexpr (is_invocable_r_v<Id, M, EmitSPIRV&, EmitContext&, const IR::Value&>) {
84 ctx.Define(inst, (emit.*method)(ctx, inst->Arg(0)));
85 } else if constexpr (is_invocable_r_v<Id, M, EmitSPIRV&, EmitContext&, const IR::Value&,
86 const IR::Value&>) {
87 ctx.Define(inst, (emit.*method)(ctx, inst->Arg(0), inst->Arg(1)));
88 } else if constexpr (is_invocable_r_v<void, M, EmitSPIRV&, EmitContext&, IR::Inst*>) {
89 (emit.*method)(ctx, inst);
90 } else if constexpr (is_invocable_r_v<void, M, EmitSPIRV&, EmitContext&>) {
91 (emit.*method)(ctx);
92 } else {
93 static_assert(false, "Bad format");
94 }
95}
96
97void EmitSPIRV::EmitInst(EmitContext& ctx, IR::Inst* inst) {
98 switch (inst->Opcode()) {
99#define OPCODE(name, result_type, ...) \
100 case IR::Opcode::name: \
101 return Invoke<&EmitSPIRV::Emit##name>(*this, ctx, inst);
102#include "shader_recompiler/frontend/ir/opcodes.inc"
103#undef OPCODE
104 }
105 throw LogicError("Invalid opcode {}", inst->Opcode());
106}
107
108void EmitSPIRV::EmitPhi(EmitContext&) {
109 throw NotImplementedException("SPIR-V Instruction");
110}
111
112void EmitSPIRV::EmitVoid(EmitContext&) {}
113
114void EmitSPIRV::EmitIdentity(EmitContext&) {
115 throw NotImplementedException("SPIR-V Instruction");
116}
117
118void EmitSPIRV::EmitGetZeroFromOp(EmitContext&) {
119 throw LogicError("Unreachable instruction");
120}
121
122void EmitSPIRV::EmitGetSignFromOp(EmitContext&) {
123 throw LogicError("Unreachable instruction");
124}
125
126void EmitSPIRV::EmitGetCarryFromOp(EmitContext&) {
127 throw LogicError("Unreachable instruction");
128}
129
130void EmitSPIRV::EmitGetOverflowFromOp(EmitContext&) {
131 throw LogicError("Unreachable instruction");
132}
133
134} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index 99cc8e08a..3f4b68a7d 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -4,18 +4,326 @@
4 4
5#pragma once 5#pragma once
6 6
7#include <sirit/sirit.h>
8
9#include <boost/container/flat_map.hpp>
10
11#include "common/common_types.h"
7#include "shader_recompiler/frontend/ir/microinstruction.h" 12#include "shader_recompiler/frontend/ir/microinstruction.h"
8#include "shader_recompiler/frontend/ir/program.h" 13#include "shader_recompiler/frontend/ir/program.h"
9 14
10namespace Shader::Backend::SPIRV { 15namespace Shader::Backend::SPIRV {
11 16
17using Sirit::Id;
18
19class DefMap {
20public:
21 void Define(IR::Inst* inst, Id def_id) {
22 const InstInfo info{.use_count{inst->UseCount()}, .def_id{def_id}};
23 const auto it{map.insert(map.end(), std::make_pair(inst, info))};
24 if (it == map.end()) {
25 throw LogicError("Defining already defined instruction");
26 }
27 }
28
29 [[nodiscard]] Id Consume(IR::Inst* inst) {
30 const auto it{map.find(inst)};
31 if (it == map.end()) {
32 throw LogicError("Consuming undefined instruction");
33 }
34 const Id def_id{it->second.def_id};
35 if (--it->second.use_count == 0) {
36 map.erase(it);
37 }
38 return def_id;
39 }
40
41private:
42 struct InstInfo {
43 int use_count;
44 Id def_id;
45 };
46
47 boost::container::flat_map<IR::Inst*, InstInfo> map;
48};
49
50class VectorTypes {
51public:
52 void Define(Sirit::Module& sirit_ctx, Id base_type, std::string_view name) {
53 defs[0] = sirit_ctx.Name(base_type, name);
54
55 std::array<char, 6> def_name;
56 for (int i = 1; i < 4; ++i) {
57 const std::string_view def_name_view(
58 def_name.data(),
59 fmt::format_to_n(def_name.data(), def_name.size(), "{}x{}", name, i + 1).size);
60 defs[i] = sirit_ctx.Name(sirit_ctx.TypeVector(base_type, i + 1), def_name_view);
61 }
62 }
63
64 [[nodiscard]] Id operator[](size_t size) const noexcept {
65 return defs[size - 1];
66 }
67
68private:
69 std::array<Id, 4> defs;
70};
71
72class EmitContext final : public Sirit::Module {
73public:
74 explicit EmitContext(IR::Program& program);
75 ~EmitContext();
76
77 [[nodiscard]] Id Def(const IR::Value& value) {
78 if (!value.IsImmediate()) {
79 return def_map.Consume(value.Inst());
80 }
81 switch (value.Type()) {
82 case IR::Type::U32:
83 return Constant(u32[1], value.U32());
84 case IR::Type::F32:
85 return Constant(f32[1], value.F32());
86 default:
87 throw NotImplementedException("Immediate type {}", value.Type());
88 }
89 }
90
91 void Define(IR::Inst* inst, Id def_id) {
92 def_map.Define(inst, def_id);
93 }
94
95 [[nodiscard]] Id BlockLabel(IR::Block* block) const {
96 const auto it{std::ranges::lower_bound(block_label_map, block, {},
97 &std::pair<IR::Block*, Id>::first)};
98 if (it == block_label_map.end()) {
99 throw LogicError("Undefined block");
100 }
101 return it->second;
102 }
103
104 Id void_id{};
105 Id u1{};
106 VectorTypes f32;
107 VectorTypes u32;
108 VectorTypes f16;
109 VectorTypes f64;
110
111 Id workgroup_id{};
112 Id local_invocation_id{};
113
114private:
115 DefMap def_map;
116 std::vector<std::pair<IR::Block*, Id>> block_label_map;
117};
118
12class EmitSPIRV { 119class EmitSPIRV {
13public: 120public:
121 explicit EmitSPIRV(IR::Program& program);
122
14private: 123private:
124 void EmitInst(EmitContext& ctx, IR::Inst* inst);
125
15 // Microinstruction emitters 126 // Microinstruction emitters
16#define OPCODE(name, result_type, ...) void Emit##name(EmitContext& ctx, IR::Inst* inst); 127 void EmitPhi(EmitContext& ctx);
17#include "shader_recompiler/frontend/ir/opcodes.inc" 128 void EmitVoid(EmitContext& ctx);
18#undef OPCODE 129 void EmitIdentity(EmitContext& ctx);
130 void EmitBranch(EmitContext& ctx, IR::Inst* inst);
131 void EmitBranchConditional(EmitContext& ctx, IR::Inst* inst);
132 void EmitExit(EmitContext& ctx);
133 void EmitReturn(EmitContext& ctx);
134 void EmitUnreachable(EmitContext& ctx);
135 void EmitGetRegister(EmitContext& ctx);
136 void EmitSetRegister(EmitContext& ctx);
137 void EmitGetPred(EmitContext& ctx);
138 void EmitSetPred(EmitContext& ctx);
139 Id EmitGetCbuf(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
140 void EmitGetAttribute(EmitContext& ctx);
141 void EmitSetAttribute(EmitContext& ctx);
142 void EmitGetAttributeIndexed(EmitContext& ctx);
143 void EmitSetAttributeIndexed(EmitContext& ctx);
144 void EmitGetZFlag(EmitContext& ctx);
145 void EmitGetSFlag(EmitContext& ctx);
146 void EmitGetCFlag(EmitContext& ctx);
147 void EmitGetOFlag(EmitContext& ctx);
148 void EmitSetZFlag(EmitContext& ctx);
149 void EmitSetSFlag(EmitContext& ctx);
150 void EmitSetCFlag(EmitContext& ctx);
151 void EmitSetOFlag(EmitContext& ctx);
152 Id EmitWorkgroupId(EmitContext& ctx);
153 Id EmitLocalInvocationId(EmitContext& ctx);
154 void EmitUndef1(EmitContext& ctx);
155 void EmitUndef8(EmitContext& ctx);
156 void EmitUndef16(EmitContext& ctx);
157 void EmitUndef32(EmitContext& ctx);
158 void EmitUndef64(EmitContext& ctx);
159 void EmitLoadGlobalU8(EmitContext& ctx);
160 void EmitLoadGlobalS8(EmitContext& ctx);
161 void EmitLoadGlobalU16(EmitContext& ctx);
162 void EmitLoadGlobalS16(EmitContext& ctx);
163 void EmitLoadGlobal32(EmitContext& ctx);
164 void EmitLoadGlobal64(EmitContext& ctx);
165 void EmitLoadGlobal128(EmitContext& ctx);
166 void EmitWriteGlobalU8(EmitContext& ctx);
167 void EmitWriteGlobalS8(EmitContext& ctx);
168 void EmitWriteGlobalU16(EmitContext& ctx);
169 void EmitWriteGlobalS16(EmitContext& ctx);
170 void EmitWriteGlobal32(EmitContext& ctx);
171 void EmitWriteGlobal64(EmitContext& ctx);
172 void EmitWriteGlobal128(EmitContext& ctx);
173 void EmitLoadStorageU8(EmitContext& ctx);
174 void EmitLoadStorageS8(EmitContext& ctx);
175 void EmitLoadStorageU16(EmitContext& ctx);
176 void EmitLoadStorageS16(EmitContext& ctx);
177 Id EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
178 void EmitLoadStorage64(EmitContext& ctx);
179 void EmitLoadStorage128(EmitContext& ctx);
180 void EmitWriteStorageU8(EmitContext& ctx);
181 void EmitWriteStorageS8(EmitContext& ctx);
182 void EmitWriteStorageU16(EmitContext& ctx);
183 void EmitWriteStorageS16(EmitContext& ctx);
184 void EmitWriteStorage32(EmitContext& ctx);
185 void EmitWriteStorage64(EmitContext& ctx);
186 void EmitWriteStorage128(EmitContext& ctx);
187 void EmitCompositeConstructU32x2(EmitContext& ctx);
188 void EmitCompositeConstructU32x3(EmitContext& ctx);
189 void EmitCompositeConstructU32x4(EmitContext& ctx);
190 void EmitCompositeExtractU32x2(EmitContext& ctx);
191 Id EmitCompositeExtractU32x3(EmitContext& ctx, Id vector, u32 index);
192 void EmitCompositeExtractU32x4(EmitContext& ctx);
193 void EmitCompositeConstructF16x2(EmitContext& ctx);
194 void EmitCompositeConstructF16x3(EmitContext& ctx);
195 void EmitCompositeConstructF16x4(EmitContext& ctx);
196 void EmitCompositeExtractF16x2(EmitContext& ctx);
197 void EmitCompositeExtractF16x3(EmitContext& ctx);
198 void EmitCompositeExtractF16x4(EmitContext& ctx);
199 void EmitCompositeConstructF32x2(EmitContext& ctx);
200 void EmitCompositeConstructF32x3(EmitContext& ctx);
201 void EmitCompositeConstructF32x4(EmitContext& ctx);
202 void EmitCompositeExtractF32x2(EmitContext& ctx);
203 void EmitCompositeExtractF32x3(EmitContext& ctx);
204 void EmitCompositeExtractF32x4(EmitContext& ctx);
205 void EmitCompositeConstructF64x2(EmitContext& ctx);
206 void EmitCompositeConstructF64x3(EmitContext& ctx);
207 void EmitCompositeConstructF64x4(EmitContext& ctx);
208 void EmitCompositeExtractF64x2(EmitContext& ctx);
209 void EmitCompositeExtractF64x3(EmitContext& ctx);
210 void EmitCompositeExtractF64x4(EmitContext& ctx);
211 void EmitSelect8(EmitContext& ctx);
212 void EmitSelect16(EmitContext& ctx);
213 void EmitSelect32(EmitContext& ctx);
214 void EmitSelect64(EmitContext& ctx);
215 void EmitBitCastU16F16(EmitContext& ctx);
216 Id EmitBitCastU32F32(EmitContext& ctx, Id value);
217 void EmitBitCastU64F64(EmitContext& ctx);
218 void EmitBitCastF16U16(EmitContext& ctx);
219 Id EmitBitCastF32U32(EmitContext& ctx, Id value);
220 void EmitBitCastF64U64(EmitContext& ctx);
221 void EmitPackUint2x32(EmitContext& ctx);
222 void EmitUnpackUint2x32(EmitContext& ctx);
223 void EmitPackFloat2x16(EmitContext& ctx);
224 void EmitUnpackFloat2x16(EmitContext& ctx);
225 void EmitPackDouble2x32(EmitContext& ctx);
226 void EmitUnpackDouble2x32(EmitContext& ctx);
227 void EmitGetZeroFromOp(EmitContext& ctx);
228 void EmitGetSignFromOp(EmitContext& ctx);
229 void EmitGetCarryFromOp(EmitContext& ctx);
230 void EmitGetOverflowFromOp(EmitContext& ctx);
231 void EmitFPAbs16(EmitContext& ctx);
232 void EmitFPAbs32(EmitContext& ctx);
233 void EmitFPAbs64(EmitContext& ctx);
234 Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
235 Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
236 Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
237 Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
238 Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
239 Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
240 void EmitFPMax32(EmitContext& ctx);
241 void EmitFPMax64(EmitContext& ctx);
242 void EmitFPMin32(EmitContext& ctx);
243 void EmitFPMin64(EmitContext& ctx);
244 Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
245 Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
246 Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
247 void EmitFPNeg16(EmitContext& ctx);
248 void EmitFPNeg32(EmitContext& ctx);
249 void EmitFPNeg64(EmitContext& ctx);
250 void EmitFPRecip32(EmitContext& ctx);
251 void EmitFPRecip64(EmitContext& ctx);
252 void EmitFPRecipSqrt32(EmitContext& ctx);
253 void EmitFPRecipSqrt64(EmitContext& ctx);
254 void EmitFPSqrt(EmitContext& ctx);
255 void EmitFPSin(EmitContext& ctx);
256 void EmitFPSinNotReduced(EmitContext& ctx);
257 void EmitFPExp2(EmitContext& ctx);
258 void EmitFPExp2NotReduced(EmitContext& ctx);
259 void EmitFPCos(EmitContext& ctx);
260 void EmitFPCosNotReduced(EmitContext& ctx);
261 void EmitFPLog2(EmitContext& ctx);
262 void EmitFPSaturate16(EmitContext& ctx);
263 void EmitFPSaturate32(EmitContext& ctx);
264 void EmitFPSaturate64(EmitContext& ctx);
265 void EmitFPRoundEven16(EmitContext& ctx);
266 void EmitFPRoundEven32(EmitContext& ctx);
267 void EmitFPRoundEven64(EmitContext& ctx);
268 void EmitFPFloor16(EmitContext& ctx);
269 void EmitFPFloor32(EmitContext& ctx);
270 void EmitFPFloor64(EmitContext& ctx);
271 void EmitFPCeil16(EmitContext& ctx);
272 void EmitFPCeil32(EmitContext& ctx);
273 void EmitFPCeil64(EmitContext& ctx);
274 void EmitFPTrunc16(EmitContext& ctx);
275 void EmitFPTrunc32(EmitContext& ctx);
276 void EmitFPTrunc64(EmitContext& ctx);
277 Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
278 void EmitIAdd64(EmitContext& ctx);
279 Id EmitISub32(EmitContext& ctx, Id a, Id b);
280 void EmitISub64(EmitContext& ctx);
281 Id EmitIMul32(EmitContext& ctx, Id a, Id b);
282 void EmitINeg32(EmitContext& ctx);
283 void EmitIAbs32(EmitContext& ctx);
284 Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
285 void EmitShiftRightLogical32(EmitContext& ctx);
286 void EmitShiftRightArithmetic32(EmitContext& ctx);
287 void EmitBitwiseAnd32(EmitContext& ctx);
288 void EmitBitwiseOr32(EmitContext& ctx);
289 void EmitBitwiseXor32(EmitContext& ctx);
290 void EmitBitFieldInsert(EmitContext& ctx);
291 void EmitBitFieldSExtract(EmitContext& ctx);
292 Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
293 void EmitSLessThan(EmitContext& ctx);
294 void EmitULessThan(EmitContext& ctx);
295 void EmitIEqual(EmitContext& ctx);
296 void EmitSLessThanEqual(EmitContext& ctx);
297 void EmitULessThanEqual(EmitContext& ctx);
298 void EmitSGreaterThan(EmitContext& ctx);
299 void EmitUGreaterThan(EmitContext& ctx);
300 void EmitINotEqual(EmitContext& ctx);
301 void EmitSGreaterThanEqual(EmitContext& ctx);
302 Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs);
303 void EmitLogicalOr(EmitContext& ctx);
304 void EmitLogicalAnd(EmitContext& ctx);
305 void EmitLogicalXor(EmitContext& ctx);
306 void EmitLogicalNot(EmitContext& ctx);
307 void EmitConvertS16F16(EmitContext& ctx);
308 void EmitConvertS16F32(EmitContext& ctx);
309 void EmitConvertS16F64(EmitContext& ctx);
310 void EmitConvertS32F16(EmitContext& ctx);
311 void EmitConvertS32F32(EmitContext& ctx);
312 void EmitConvertS32F64(EmitContext& ctx);
313 void EmitConvertS64F16(EmitContext& ctx);
314 void EmitConvertS64F32(EmitContext& ctx);
315 void EmitConvertS64F64(EmitContext& ctx);
316 void EmitConvertU16F16(EmitContext& ctx);
317 void EmitConvertU16F32(EmitContext& ctx);
318 void EmitConvertU16F64(EmitContext& ctx);
319 void EmitConvertU32F16(EmitContext& ctx);
320 void EmitConvertU32F32(EmitContext& ctx);
321 void EmitConvertU32F64(EmitContext& ctx);
322 void EmitConvertU64F16(EmitContext& ctx);
323 void EmitConvertU64F32(EmitContext& ctx);
324 void EmitConvertU64F64(EmitContext& ctx);
325 void EmitConvertU64U32(EmitContext& ctx);
326 void EmitConvertU32U64(EmitContext& ctx);
19}; 327};
20 328
21} // namespace Shader::Backend::SPIRV 329} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp
new file mode 100644
index 000000000..447df5b8c
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp
@@ -0,0 +1,57 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "shader_recompiler/backend/spirv/emit_spirv.h"
6
7namespace Shader::Backend::SPIRV {
8
9void EmitSPIRV::EmitBitCastU16F16(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction");
11}
12
13Id EmitSPIRV::EmitBitCastU32F32(EmitContext& ctx, Id value) {
14 return ctx.OpBitcast(ctx.u32[1], value);
15}
16
17void EmitSPIRV::EmitBitCastU64F64(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction");
19}
20
21void EmitSPIRV::EmitBitCastF16U16(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction");
23}
24
25Id EmitSPIRV::EmitBitCastF32U32(EmitContext& ctx, Id value) {
26 return ctx.OpBitcast(ctx.f32[1], value);
27}
28
29void EmitSPIRV::EmitBitCastF64U64(EmitContext&) {
30 throw NotImplementedException("SPIR-V Instruction");
31}
32
33void EmitSPIRV::EmitPackUint2x32(EmitContext&) {
34 throw NotImplementedException("SPIR-V Instruction");
35}
36
37void EmitSPIRV::EmitUnpackUint2x32(EmitContext&) {
38 throw NotImplementedException("SPIR-V Instruction");
39}
40
41void EmitSPIRV::EmitPackFloat2x16(EmitContext&) {
42 throw NotImplementedException("SPIR-V Instruction");
43}
44
45void EmitSPIRV::EmitUnpackFloat2x16(EmitContext&) {
46 throw NotImplementedException("SPIR-V Instruction");
47}
48
49void EmitSPIRV::EmitPackDouble2x32(EmitContext&) {
50 throw NotImplementedException("SPIR-V Instruction");
51}
52
53void EmitSPIRV::EmitUnpackDouble2x32(EmitContext&) {
54 throw NotImplementedException("SPIR-V Instruction");
55}
56
57} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp
new file mode 100644
index 000000000..b190cf876
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp
@@ -0,0 +1,105 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "shader_recompiler/backend/spirv/emit_spirv.h"
6
7namespace Shader::Backend::SPIRV {
8
9void EmitSPIRV::EmitCompositeConstructU32x2(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction");
11}
12
13void EmitSPIRV::EmitCompositeConstructU32x3(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction");
15}
16
17void EmitSPIRV::EmitCompositeConstructU32x4(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction");
19}
20
21void EmitSPIRV::EmitCompositeExtractU32x2(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction");
23}
24
25Id EmitSPIRV::EmitCompositeExtractU32x3(EmitContext& ctx, Id vector, u32 index) {
26 return ctx.OpCompositeExtract(ctx.u32[1], vector, index);
27}
28
29void EmitSPIRV::EmitCompositeExtractU32x4(EmitContext&) {
30 throw NotImplementedException("SPIR-V Instruction");
31}
32
33void EmitSPIRV::EmitCompositeConstructF16x2(EmitContext&) {
34 throw NotImplementedException("SPIR-V Instruction");
35}
36
37void EmitSPIRV::EmitCompositeConstructF16x3(EmitContext&) {
38 throw NotImplementedException("SPIR-V Instruction");
39}
40
41void EmitSPIRV::EmitCompositeConstructF16x4(EmitContext&) {
42 throw NotImplementedException("SPIR-V Instruction");
43}
44
45void EmitSPIRV::EmitCompositeExtractF16x2(EmitContext&) {
46 throw NotImplementedException("SPIR-V Instruction");
47}
48
49void EmitSPIRV::EmitCompositeExtractF16x3(EmitContext&) {
50 throw NotImplementedException("SPIR-V Instruction");
51}
52
53void EmitSPIRV::EmitCompositeExtractF16x4(EmitContext&) {
54 throw NotImplementedException("SPIR-V Instruction");
55}
56
57void EmitSPIRV::EmitCompositeConstructF32x2(EmitContext&) {
58 throw NotImplementedException("SPIR-V Instruction");
59}
60
61void EmitSPIRV::EmitCompositeConstructF32x3(EmitContext&) {
62 throw NotImplementedException("SPIR-V Instruction");
63}
64
65void EmitSPIRV::EmitCompositeConstructF32x4(EmitContext&) {
66 throw NotImplementedException("SPIR-V Instruction");
67}
68
69void EmitSPIRV::EmitCompositeExtractF32x2(EmitContext&) {
70 throw NotImplementedException("SPIR-V Instruction");
71}
72
73void EmitSPIRV::EmitCompositeExtractF32x3(EmitContext&) {
74 throw NotImplementedException("SPIR-V Instruction");
75}
76
77void EmitSPIRV::EmitCompositeExtractF32x4(EmitContext&) {
78 throw NotImplementedException("SPIR-V Instruction");
79}
80
81void EmitSPIRV::EmitCompositeConstructF64x2(EmitContext&) {
82 throw NotImplementedException("SPIR-V Instruction");
83}
84
85void EmitSPIRV::EmitCompositeConstructF64x3(EmitContext&) {
86 throw NotImplementedException("SPIR-V Instruction");
87}
88
89void EmitSPIRV::EmitCompositeConstructF64x4(EmitContext&) {
90 throw NotImplementedException("SPIR-V Instruction");
91}
92
93void EmitSPIRV::EmitCompositeExtractF64x2(EmitContext&) {
94 throw NotImplementedException("SPIR-V Instruction");
95}
96
97void EmitSPIRV::EmitCompositeExtractF64x3(EmitContext&) {
98 throw NotImplementedException("SPIR-V Instruction");
99}
100
101void EmitSPIRV::EmitCompositeExtractF64x4(EmitContext&) {
102 throw NotImplementedException("SPIR-V Instruction");
103}
104
105} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
new file mode 100644
index 000000000..b121305ea
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
@@ -0,0 +1,102 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "shader_recompiler/backend/spirv/emit_spirv.h"
6
7namespace Shader::Backend::SPIRV {
8
9void EmitSPIRV::EmitGetRegister(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction");
11}
12
13void EmitSPIRV::EmitSetRegister(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction");
15}
16
17void EmitSPIRV::EmitGetPred(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction");
19}
20
21void EmitSPIRV::EmitSetPred(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction");
23}
24
25Id EmitSPIRV::EmitGetCbuf(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
26 if (!binding.IsImmediate()) {
27 throw NotImplementedException("Constant buffer indexing");
28 }
29 if (!offset.IsImmediate()) {
30 throw NotImplementedException("Variable constant buffer offset");
31 }
32 return ctx.Name(ctx.OpUndef(ctx.u32[1]), "unimplemented_cbuf");
33}
34
35void EmitSPIRV::EmitGetAttribute(EmitContext&) {
36 throw NotImplementedException("SPIR-V Instruction");
37}
38
39void EmitSPIRV::EmitSetAttribute(EmitContext&) {
40 throw NotImplementedException("SPIR-V Instruction");
41}
42
43void EmitSPIRV::EmitGetAttributeIndexed(EmitContext&) {
44 throw NotImplementedException("SPIR-V Instruction");
45}
46
47void EmitSPIRV::EmitSetAttributeIndexed(EmitContext&) {
48 throw NotImplementedException("SPIR-V Instruction");
49}
50
51void EmitSPIRV::EmitGetZFlag(EmitContext&) {
52 throw NotImplementedException("SPIR-V Instruction");
53}
54
55void EmitSPIRV::EmitGetSFlag(EmitContext&) {
56 throw NotImplementedException("SPIR-V Instruction");
57}
58
59void EmitSPIRV::EmitGetCFlag(EmitContext&) {
60 throw NotImplementedException("SPIR-V Instruction");
61}
62
63void EmitSPIRV::EmitGetOFlag(EmitContext&) {
64 throw NotImplementedException("SPIR-V Instruction");
65}
66
67void EmitSPIRV::EmitSetZFlag(EmitContext&) {
68 throw NotImplementedException("SPIR-V Instruction");
69}
70
71void EmitSPIRV::EmitSetSFlag(EmitContext&) {
72 throw NotImplementedException("SPIR-V Instruction");
73}
74
75void EmitSPIRV::EmitSetCFlag(EmitContext&) {
76 throw NotImplementedException("SPIR-V Instruction");
77}
78
79void EmitSPIRV::EmitSetOFlag(EmitContext&) {
80 throw NotImplementedException("SPIR-V Instruction");
81}
82
83Id EmitSPIRV::EmitWorkgroupId(EmitContext& ctx) {
84 if (ctx.workgroup_id.value == 0) {
85 ctx.workgroup_id = ctx.AddGlobalVariable(
86 ctx.TypePointer(spv::StorageClass::Input, ctx.u32[3]), spv::StorageClass::Input);
87 ctx.Decorate(ctx.workgroup_id, spv::Decoration::BuiltIn, spv::BuiltIn::WorkgroupId);
88 }
89 return ctx.OpLoad(ctx.u32[3], ctx.workgroup_id);
90}
91
92Id EmitSPIRV::EmitLocalInvocationId(EmitContext& ctx) {
93 if (ctx.local_invocation_id.value == 0) {
94 ctx.local_invocation_id = ctx.AddGlobalVariable(
95 ctx.TypePointer(spv::StorageClass::Input, ctx.u32[3]), spv::StorageClass::Input);
96 ctx.Decorate(ctx.local_invocation_id, spv::Decoration::BuiltIn,
97 spv::BuiltIn::LocalInvocationId);
98 }
99 return ctx.OpLoad(ctx.u32[3], ctx.local_invocation_id);
100}
101
102} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp
new file mode 100644
index 000000000..770fe113c
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp
@@ -0,0 +1,30 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "shader_recompiler/backend/spirv/emit_spirv.h"
6
7namespace Shader::Backend::SPIRV {
8
9void EmitSPIRV::EmitBranch(EmitContext& ctx, IR::Inst* inst) {
10 ctx.OpBranch(ctx.BlockLabel(inst->Arg(0).Label()));
11}
12
13void EmitSPIRV::EmitBranchConditional(EmitContext& ctx, IR::Inst* inst) {
14 ctx.OpBranchConditional(ctx.Def(inst->Arg(0)), ctx.BlockLabel(inst->Arg(1).Label()),
15 ctx.BlockLabel(inst->Arg(2).Label()));
16}
17
18void EmitSPIRV::EmitExit(EmitContext& ctx) {
19 ctx.OpReturn();
20}
21
22void EmitSPIRV::EmitReturn(EmitContext&) {
23 throw NotImplementedException("SPIR-V Instruction");
24}
25
26void EmitSPIRV::EmitUnreachable(EmitContext&) {
27 throw NotImplementedException("SPIR-V Instruction");
28}
29
30} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp
new file mode 100644
index 000000000..9c39537e2
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp
@@ -0,0 +1,220 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "shader_recompiler/backend/spirv/emit_spirv.h"
6#include "shader_recompiler/frontend/ir/modifiers.h"
7
8namespace Shader::Backend::SPIRV {
9namespace {
10Id Decorate(EmitContext& ctx, IR::Inst* inst, Id op) {
11 const auto flags{inst->Flags<IR::FpControl>()};
12 if (flags.no_contraction) {
13 ctx.Decorate(op, spv::Decoration::NoContraction);
14 }
15 switch (flags.rounding) {
16 case IR::FpRounding::RN:
17 break;
18 case IR::FpRounding::RM:
19 ctx.Decorate(op, spv::Decoration::FPRoundingMode, spv::FPRoundingMode::RTN);
20 break;
21 case IR::FpRounding::RP:
22 ctx.Decorate(op, spv::Decoration::FPRoundingMode, spv::FPRoundingMode::RTP);
23 break;
24 case IR::FpRounding::RZ:
25 ctx.Decorate(op, spv::Decoration::FPRoundingMode, spv::FPRoundingMode::RTZ);
26 break;
27 }
28 if (flags.fmz_mode != IR::FmzMode::FTZ) {
29 throw NotImplementedException("Denorm management not implemented");
30 }
31 return op;
32}
33
34} // Anonymous namespace
35
36void EmitSPIRV::EmitFPAbs16(EmitContext&) {
37 throw NotImplementedException("SPIR-V Instruction");
38}
39
40void EmitSPIRV::EmitFPAbs32(EmitContext&) {
41 throw NotImplementedException("SPIR-V Instruction");
42}
43
44void EmitSPIRV::EmitFPAbs64(EmitContext&) {
45 throw NotImplementedException("SPIR-V Instruction");
46}
47
48Id EmitSPIRV::EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
49 return Decorate(ctx, inst, ctx.OpFAdd(ctx.f16[1], a, b));
50}
51
52Id EmitSPIRV::EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
53 return Decorate(ctx, inst, ctx.OpFAdd(ctx.f32[1], a, b));
54}
55
56Id EmitSPIRV::EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
57 return Decorate(ctx, inst, ctx.OpFAdd(ctx.f64[1], a, b));
58}
59
60Id EmitSPIRV::EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
61 return Decorate(ctx, inst, ctx.OpFma(ctx.f16[1], a, b, c));
62}
63
64Id EmitSPIRV::EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
65 return Decorate(ctx, inst, ctx.OpFma(ctx.f32[1], a, b, c));
66}
67
68Id EmitSPIRV::EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
69 return Decorate(ctx, inst, ctx.OpFma(ctx.f64[1], a, b, c));
70}
71
72void EmitSPIRV::EmitFPMax32(EmitContext&) {
73 throw NotImplementedException("SPIR-V Instruction");
74}
75
76void EmitSPIRV::EmitFPMax64(EmitContext&) {
77 throw NotImplementedException("SPIR-V Instruction");
78}
79
80void EmitSPIRV::EmitFPMin32(EmitContext&) {
81 throw NotImplementedException("SPIR-V Instruction");
82}
83
84void EmitSPIRV::EmitFPMin64(EmitContext&) {
85 throw NotImplementedException("SPIR-V Instruction");
86}
87
88Id EmitSPIRV::EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
89 return Decorate(ctx, inst, ctx.OpFMul(ctx.f16[1], a, b));
90}
91
92Id EmitSPIRV::EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
93 return Decorate(ctx, inst, ctx.OpFMul(ctx.f32[1], a, b));
94}
95
96Id EmitSPIRV::EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
97 return Decorate(ctx, inst, ctx.OpFMul(ctx.f64[1], a, b));
98}
99
100void EmitSPIRV::EmitFPNeg16(EmitContext&) {
101 throw NotImplementedException("SPIR-V Instruction");
102}
103
104void EmitSPIRV::EmitFPNeg32(EmitContext&) {
105 throw NotImplementedException("SPIR-V Instruction");
106}
107
108void EmitSPIRV::EmitFPNeg64(EmitContext&) {
109 throw NotImplementedException("SPIR-V Instruction");
110}
111
112void EmitSPIRV::EmitFPRecip32(EmitContext&) {
113 throw NotImplementedException("SPIR-V Instruction");
114}
115
116void EmitSPIRV::EmitFPRecip64(EmitContext&) {
117 throw NotImplementedException("SPIR-V Instruction");
118}
119
120void EmitSPIRV::EmitFPRecipSqrt32(EmitContext&) {
121 throw NotImplementedException("SPIR-V Instruction");
122}
123
124void EmitSPIRV::EmitFPRecipSqrt64(EmitContext&) {
125 throw NotImplementedException("SPIR-V Instruction");
126}
127
128void EmitSPIRV::EmitFPSqrt(EmitContext&) {
129 throw NotImplementedException("SPIR-V Instruction");
130}
131
132void EmitSPIRV::EmitFPSin(EmitContext&) {
133 throw NotImplementedException("SPIR-V Instruction");
134}
135
136void EmitSPIRV::EmitFPSinNotReduced(EmitContext&) {
137 throw NotImplementedException("SPIR-V Instruction");
138}
139
140void EmitSPIRV::EmitFPExp2(EmitContext&) {
141 throw NotImplementedException("SPIR-V Instruction");
142}
143
144void EmitSPIRV::EmitFPExp2NotReduced(EmitContext&) {
145 throw NotImplementedException("SPIR-V Instruction");
146}
147
148void EmitSPIRV::EmitFPCos(EmitContext&) {
149 throw NotImplementedException("SPIR-V Instruction");
150}
151
152void EmitSPIRV::EmitFPCosNotReduced(EmitContext&) {
153 throw NotImplementedException("SPIR-V Instruction");
154}
155
156void EmitSPIRV::EmitFPLog2(EmitContext&) {
157 throw NotImplementedException("SPIR-V Instruction");
158}
159
160void EmitSPIRV::EmitFPSaturate16(EmitContext&) {
161 throw NotImplementedException("SPIR-V Instruction");
162}
163
164void EmitSPIRV::EmitFPSaturate32(EmitContext&) {
165 throw NotImplementedException("SPIR-V Instruction");
166}
167
168void EmitSPIRV::EmitFPSaturate64(EmitContext&) {
169 throw NotImplementedException("SPIR-V Instruction");
170}
171
172void EmitSPIRV::EmitFPRoundEven16(EmitContext&) {
173 throw NotImplementedException("SPIR-V Instruction");
174}
175
176void EmitSPIRV::EmitFPRoundEven32(EmitContext&) {
177 throw NotImplementedException("SPIR-V Instruction");
178}
179
180void EmitSPIRV::EmitFPRoundEven64(EmitContext&) {
181 throw NotImplementedException("SPIR-V Instruction");
182}
183
184void EmitSPIRV::EmitFPFloor16(EmitContext&) {
185 throw NotImplementedException("SPIR-V Instruction");
186}
187
188void EmitSPIRV::EmitFPFloor32(EmitContext&) {
189 throw NotImplementedException("SPIR-V Instruction");
190}
191
192void EmitSPIRV::EmitFPFloor64(EmitContext&) {
193 throw NotImplementedException("SPIR-V Instruction");
194}
195
196void EmitSPIRV::EmitFPCeil16(EmitContext&) {
197 throw NotImplementedException("SPIR-V Instruction");
198}
199
200void EmitSPIRV::EmitFPCeil32(EmitContext&) {
201 throw NotImplementedException("SPIR-V Instruction");
202}
203
204void EmitSPIRV::EmitFPCeil64(EmitContext&) {
205 throw NotImplementedException("SPIR-V Instruction");
206}
207
208void EmitSPIRV::EmitFPTrunc16(EmitContext&) {
209 throw NotImplementedException("SPIR-V Instruction");
210}
211
212void EmitSPIRV::EmitFPTrunc32(EmitContext&) {
213 throw NotImplementedException("SPIR-V Instruction");
214}
215
216void EmitSPIRV::EmitFPTrunc64(EmitContext&) {
217 throw NotImplementedException("SPIR-V Instruction");
218}
219
220} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
new file mode 100644
index 000000000..3ef4f3d78
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -0,0 +1,132 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "shader_recompiler/backend/spirv/emit_spirv.h"
6
7namespace Shader::Backend::SPIRV {
8
9Id EmitSPIRV::EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
10 if (inst->HasAssociatedPseudoOperation()) {
11 throw NotImplementedException("Pseudo-operations on IAdd32");
12 }
13 return ctx.OpIAdd(ctx.u32[1], a, b);
14}
15
16void EmitSPIRV::EmitIAdd64(EmitContext&) {
17 throw NotImplementedException("SPIR-V Instruction");
18}
19
20Id EmitSPIRV::EmitISub32(EmitContext& ctx, Id a, Id b) {
21 return ctx.OpISub(ctx.u32[1], a, b);
22}
23
24void EmitSPIRV::EmitISub64(EmitContext&) {
25 throw NotImplementedException("SPIR-V Instruction");
26}
27
28Id EmitSPIRV::EmitIMul32(EmitContext& ctx, Id a, Id b) {
29 return ctx.OpIMul(ctx.u32[1], a, b);
30}
31
32void EmitSPIRV::EmitINeg32(EmitContext&) {
33 throw NotImplementedException("SPIR-V Instruction");
34}
35
36void EmitSPIRV::EmitIAbs32(EmitContext&) {
37 throw NotImplementedException("SPIR-V Instruction");
38}
39
40Id EmitSPIRV::EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
41 return ctx.OpShiftLeftLogical(ctx.u32[1], base, shift);
42}
43
44void EmitSPIRV::EmitShiftRightLogical32(EmitContext&) {
45 throw NotImplementedException("SPIR-V Instruction");
46}
47
48void EmitSPIRV::EmitShiftRightArithmetic32(EmitContext&) {
49 throw NotImplementedException("SPIR-V Instruction");
50}
51
52void EmitSPIRV::EmitBitwiseAnd32(EmitContext&) {
53 throw NotImplementedException("SPIR-V Instruction");
54}
55
56void EmitSPIRV::EmitBitwiseOr32(EmitContext&) {
57 throw NotImplementedException("SPIR-V Instruction");
58}
59
60void EmitSPIRV::EmitBitwiseXor32(EmitContext&) {
61 throw NotImplementedException("SPIR-V Instruction");
62}
63
64void EmitSPIRV::EmitBitFieldInsert(EmitContext&) {
65 throw NotImplementedException("SPIR-V Instruction");
66}
67
68void EmitSPIRV::EmitBitFieldSExtract(EmitContext&) {
69 throw NotImplementedException("SPIR-V Instruction");
70}
71
72Id EmitSPIRV::EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
73 return ctx.OpBitFieldUExtract(ctx.u32[1], base, offset, count);
74}
75
76void EmitSPIRV::EmitSLessThan(EmitContext&) {
77 throw NotImplementedException("SPIR-V Instruction");
78}
79
80void EmitSPIRV::EmitULessThan(EmitContext&) {
81 throw NotImplementedException("SPIR-V Instruction");
82}
83
84void EmitSPIRV::EmitIEqual(EmitContext&) {
85 throw NotImplementedException("SPIR-V Instruction");
86}
87
88void EmitSPIRV::EmitSLessThanEqual(EmitContext&) {
89 throw NotImplementedException("SPIR-V Instruction");
90}
91
92void EmitSPIRV::EmitULessThanEqual(EmitContext&) {
93 throw NotImplementedException("SPIR-V Instruction");
94}
95
96void EmitSPIRV::EmitSGreaterThan(EmitContext&) {
97 throw NotImplementedException("SPIR-V Instruction");
98}
99
100void EmitSPIRV::EmitUGreaterThan(EmitContext&) {
101 throw NotImplementedException("SPIR-V Instruction");
102}
103
104void EmitSPIRV::EmitINotEqual(EmitContext&) {
105 throw NotImplementedException("SPIR-V Instruction");
106}
107
108void EmitSPIRV::EmitSGreaterThanEqual(EmitContext&) {
109 throw NotImplementedException("SPIR-V Instruction");
110}
111
112Id EmitSPIRV::EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
113 return ctx.OpUGreaterThanEqual(ctx.u1, lhs, rhs);
114}
115
116void EmitSPIRV::EmitLogicalOr(EmitContext&) {
117 throw NotImplementedException("SPIR-V Instruction");
118}
119
120void EmitSPIRV::EmitLogicalAnd(EmitContext&) {
121 throw NotImplementedException("SPIR-V Instruction");
122}
123
124void EmitSPIRV::EmitLogicalXor(EmitContext&) {
125 throw NotImplementedException("SPIR-V Instruction");
126}
127
128void EmitSPIRV::EmitLogicalNot(EmitContext&) {
129 throw NotImplementedException("SPIR-V Instruction");
130}
131
132} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp
new file mode 100644
index 000000000..7b43c4ed8
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp
@@ -0,0 +1,89 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "shader_recompiler/backend/spirv/emit_spirv.h"
6
7namespace Shader::Backend::SPIRV {
8
9void EmitSPIRV::EmitConvertS16F16(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction");
11}
12
13void EmitSPIRV::EmitConvertS16F32(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction");
15}
16
17void EmitSPIRV::EmitConvertS16F64(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction");
19}
20
21void EmitSPIRV::EmitConvertS32F16(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction");
23}
24
25void EmitSPIRV::EmitConvertS32F32(EmitContext&) {
26 throw NotImplementedException("SPIR-V Instruction");
27}
28
29void EmitSPIRV::EmitConvertS32F64(EmitContext&) {
30 throw NotImplementedException("SPIR-V Instruction");
31}
32
33void EmitSPIRV::EmitConvertS64F16(EmitContext&) {
34 throw NotImplementedException("SPIR-V Instruction");
35}
36
37void EmitSPIRV::EmitConvertS64F32(EmitContext&) {
38 throw NotImplementedException("SPIR-V Instruction");
39}
40
41void EmitSPIRV::EmitConvertS64F64(EmitContext&) {
42 throw NotImplementedException("SPIR-V Instruction");
43}
44
45void EmitSPIRV::EmitConvertU16F16(EmitContext&) {
46 throw NotImplementedException("SPIR-V Instruction");
47}
48
49void EmitSPIRV::EmitConvertU16F32(EmitContext&) {
50 throw NotImplementedException("SPIR-V Instruction");
51}
52
53void EmitSPIRV::EmitConvertU16F64(EmitContext&) {
54 throw NotImplementedException("SPIR-V Instruction");
55}
56
57void EmitSPIRV::EmitConvertU32F16(EmitContext&) {
58 throw NotImplementedException("SPIR-V Instruction");
59}
60
61void EmitSPIRV::EmitConvertU32F32(EmitContext&) {
62 throw NotImplementedException("SPIR-V Instruction");
63}
64
65void EmitSPIRV::EmitConvertU32F64(EmitContext&) {
66 throw NotImplementedException("SPIR-V Instruction");
67}
68
69void EmitSPIRV::EmitConvertU64F16(EmitContext&) {
70 throw NotImplementedException("SPIR-V Instruction");
71}
72
73void EmitSPIRV::EmitConvertU64F32(EmitContext&) {
74 throw NotImplementedException("SPIR-V Instruction");
75}
76
77void EmitSPIRV::EmitConvertU64F64(EmitContext&) {
78 throw NotImplementedException("SPIR-V Instruction");
79}
80
81void EmitSPIRV::EmitConvertU64U32(EmitContext&) {
82 throw NotImplementedException("SPIR-V Instruction");
83}
84
85void EmitSPIRV::EmitConvertU32U64(EmitContext&) {
86 throw NotImplementedException("SPIR-V Instruction");
87}
88
89} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_memory.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_memory.cpp
new file mode 100644
index 000000000..21a0d72fa
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_memory.cpp
@@ -0,0 +1,125 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "shader_recompiler/backend/spirv/emit_spirv.h"
6
7namespace Shader::Backend::SPIRV {
8
9void EmitSPIRV::EmitLoadGlobalU8(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction");
11}
12
13void EmitSPIRV::EmitLoadGlobalS8(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction");
15}
16
17void EmitSPIRV::EmitLoadGlobalU16(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction");
19}
20
21void EmitSPIRV::EmitLoadGlobalS16(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction");
23}
24
25void EmitSPIRV::EmitLoadGlobal32(EmitContext&) {
26 throw NotImplementedException("SPIR-V Instruction");
27}
28
29void EmitSPIRV::EmitLoadGlobal64(EmitContext&) {
30 throw NotImplementedException("SPIR-V Instruction");
31}
32
33void EmitSPIRV::EmitLoadGlobal128(EmitContext&) {
34 throw NotImplementedException("SPIR-V Instruction");
35}
36
37void EmitSPIRV::EmitWriteGlobalU8(EmitContext&) {
38 throw NotImplementedException("SPIR-V Instruction");
39}
40
41void EmitSPIRV::EmitWriteGlobalS8(EmitContext&) {
42 throw NotImplementedException("SPIR-V Instruction");
43}
44
45void EmitSPIRV::EmitWriteGlobalU16(EmitContext&) {
46 throw NotImplementedException("SPIR-V Instruction");
47}
48
49void EmitSPIRV::EmitWriteGlobalS16(EmitContext&) {
50 throw NotImplementedException("SPIR-V Instruction");
51}
52
53void EmitSPIRV::EmitWriteGlobal32(EmitContext&) {
54 throw NotImplementedException("SPIR-V Instruction");
55}
56
57void EmitSPIRV::EmitWriteGlobal64(EmitContext&) {
58 throw NotImplementedException("SPIR-V Instruction");
59}
60
61void EmitSPIRV::EmitWriteGlobal128(EmitContext&) {
62 throw NotImplementedException("SPIR-V Instruction");
63}
64
65void EmitSPIRV::EmitLoadStorageU8(EmitContext&) {
66 throw NotImplementedException("SPIR-V Instruction");
67}
68
69void EmitSPIRV::EmitLoadStorageS8(EmitContext&) {
70 throw NotImplementedException("SPIR-V Instruction");
71}
72
73void EmitSPIRV::EmitLoadStorageU16(EmitContext&) {
74 throw NotImplementedException("SPIR-V Instruction");
75}
76
77void EmitSPIRV::EmitLoadStorageS16(EmitContext&) {
78 throw NotImplementedException("SPIR-V Instruction");
79}
80
81Id EmitSPIRV::EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding,
82 [[maybe_unused]] const IR::Value& offset) {
83 if (!binding.IsImmediate()) {
84 throw NotImplementedException("Storage buffer indexing");
85 }
86 return ctx.Name(ctx.OpUndef(ctx.u32[1]), "unimplemented_sbuf");
87}
88
89void EmitSPIRV::EmitLoadStorage64(EmitContext&) {
90 throw NotImplementedException("SPIR-V Instruction");
91}
92
93void EmitSPIRV::EmitLoadStorage128(EmitContext&) {
94 throw NotImplementedException("SPIR-V Instruction");
95}
96
97void EmitSPIRV::EmitWriteStorageU8(EmitContext&) {
98 throw NotImplementedException("SPIR-V Instruction");
99}
100
101void EmitSPIRV::EmitWriteStorageS8(EmitContext&) {
102 throw NotImplementedException("SPIR-V Instruction");
103}
104
105void EmitSPIRV::EmitWriteStorageU16(EmitContext&) {
106 throw NotImplementedException("SPIR-V Instruction");
107}
108
109void EmitSPIRV::EmitWriteStorageS16(EmitContext&) {
110 throw NotImplementedException("SPIR-V Instruction");
111}
112
113void EmitSPIRV::EmitWriteStorage32(EmitContext& ctx) {
114 ctx.Name(ctx.OpUndef(ctx.u32[1]), "unimplemented_sbuf_store");
115}
116
117void EmitSPIRV::EmitWriteStorage64(EmitContext&) {
118 throw NotImplementedException("SPIR-V Instruction");
119}
120
121void EmitSPIRV::EmitWriteStorage128(EmitContext&) {
122 throw NotImplementedException("SPIR-V Instruction");
123}
124
125} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
new file mode 100644
index 000000000..40a856f72
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
@@ -0,0 +1,25 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "shader_recompiler/backend/spirv/emit_spirv.h"
6
7namespace Shader::Backend::SPIRV {
8
9void EmitSPIRV::EmitSelect8(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction");
11}
12
13void EmitSPIRV::EmitSelect16(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction");
15}
16
17void EmitSPIRV::EmitSelect32(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction");
19}
20
21void EmitSPIRV::EmitSelect64(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction");
23}
24
25} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp
new file mode 100644
index 000000000..3850b072c
--- /dev/null
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp
@@ -0,0 +1,29 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "shader_recompiler/backend/spirv/emit_spirv.h"
6
7namespace Shader::Backend::SPIRV {
8
9void EmitSPIRV::EmitUndef1(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction");
11}
12
13void EmitSPIRV::EmitUndef8(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction");
15}
16
17void EmitSPIRV::EmitUndef16(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction");
19}
20
21void EmitSPIRV::EmitUndef32(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction");
23}
24
25void EmitSPIRV::EmitUndef64(EmitContext&) {
26 throw NotImplementedException("SPIR-V Instruction");
27}
28
29} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index 9d7dc034c..ada0be834 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -130,27 +130,27 @@ void IREmitter::SetAttribute(IR::Attribute attribute, const F32& value) {
130} 130}
131 131
132U32 IREmitter::WorkgroupIdX() { 132U32 IREmitter::WorkgroupIdX() {
133 return Inst<U32>(Opcode::WorkgroupIdX); 133 return U32{CompositeExtract(Inst(Opcode::WorkgroupId), 0)};
134} 134}
135 135
136U32 IREmitter::WorkgroupIdY() { 136U32 IREmitter::WorkgroupIdY() {
137 return Inst<U32>(Opcode::WorkgroupIdY); 137 return U32{CompositeExtract(Inst(Opcode::WorkgroupId), 1)};
138} 138}
139 139
140U32 IREmitter::WorkgroupIdZ() { 140U32 IREmitter::WorkgroupIdZ() {
141 return Inst<U32>(Opcode::WorkgroupIdZ); 141 return U32{CompositeExtract(Inst(Opcode::WorkgroupId), 2)};
142} 142}
143 143
144U32 IREmitter::LocalInvocationIdX() { 144U32 IREmitter::LocalInvocationIdX() {
145 return Inst<U32>(Opcode::LocalInvocationIdX); 145 return U32{CompositeExtract(Inst(Opcode::LocalInvocationId), 0)};
146} 146}
147 147
148U32 IREmitter::LocalInvocationIdY() { 148U32 IREmitter::LocalInvocationIdY() {
149 return Inst<U32>(Opcode::LocalInvocationIdY); 149 return U32{CompositeExtract(Inst(Opcode::LocalInvocationId), 1)};
150} 150}
151 151
152U32 IREmitter::LocalInvocationIdZ() { 152U32 IREmitter::LocalInvocationIdZ() {
153 return Inst<U32>(Opcode::LocalInvocationIdZ); 153 return U32{CompositeExtract(Inst(Opcode::LocalInvocationId), 2)};
154} 154}
155 155
156U32 IREmitter::LoadGlobalU8(const U64& address) { 156U32 IREmitter::LoadGlobalU8(const U64& address) {
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc
index 82b04f37c..5dc65f2df 100644
--- a/src/shader_recompiler/frontend/ir/opcodes.inc
+++ b/src/shader_recompiler/frontend/ir/opcodes.inc
@@ -21,9 +21,9 @@ OPCODE(GetPred, U1, Pred
21OPCODE(SetPred, Void, Pred, U1, ) 21OPCODE(SetPred, Void, Pred, U1, )
22OPCODE(GetCbuf, U32, U32, U32, ) 22OPCODE(GetCbuf, U32, U32, U32, )
23OPCODE(GetAttribute, U32, Attribute, ) 23OPCODE(GetAttribute, U32, Attribute, )
24OPCODE(SetAttribute, U32, Attribute, ) 24OPCODE(SetAttribute, Void, Attribute, U32, )
25OPCODE(GetAttributeIndexed, U32, U32, ) 25OPCODE(GetAttributeIndexed, U32, U32, )
26OPCODE(SetAttributeIndexed, U32, U32, ) 26OPCODE(SetAttributeIndexed, Void, U32, U32, )
27OPCODE(GetZFlag, U1, Void, ) 27OPCODE(GetZFlag, U1, Void, )
28OPCODE(GetSFlag, U1, Void, ) 28OPCODE(GetSFlag, U1, Void, )
29OPCODE(GetCFlag, U1, Void, ) 29OPCODE(GetCFlag, U1, Void, )
@@ -32,12 +32,8 @@ OPCODE(SetZFlag, Void, U1,
32OPCODE(SetSFlag, Void, U1, ) 32OPCODE(SetSFlag, Void, U1, )
33OPCODE(SetCFlag, Void, U1, ) 33OPCODE(SetCFlag, Void, U1, )
34OPCODE(SetOFlag, Void, U1, ) 34OPCODE(SetOFlag, Void, U1, )
35OPCODE(WorkgroupIdX, U32, ) 35OPCODE(WorkgroupId, U32x3, )
36OPCODE(WorkgroupIdY, U32, ) 36OPCODE(LocalInvocationId, U32x3, )
37OPCODE(WorkgroupIdZ, U32, )
38OPCODE(LocalInvocationIdX, U32, )
39OPCODE(LocalInvocationIdY, U32, )
40OPCODE(LocalInvocationIdZ, U32, )
41 37
42// Undefined 38// Undefined
43OPCODE(Undef1, U1, ) 39OPCODE(Undef1, U1, )
diff --git a/src/shader_recompiler/frontend/maxwell/translate/translate.cpp b/src/shader_recompiler/frontend/maxwell/translate/translate.cpp
index dcc3f6c0e..7e6bb07a2 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/translate.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/translate.cpp
@@ -11,15 +11,15 @@
11 11
12namespace Shader::Maxwell { 12namespace Shader::Maxwell {
13 13
14template <auto visitor_method> 14template <auto method>
15static void Invoke(TranslatorVisitor& visitor, Location pc, u64 insn) { 15static void Invoke(TranslatorVisitor& visitor, Location pc, u64 insn) {
16 using MethodType = decltype(visitor_method); 16 using MethodType = decltype(method);
17 if constexpr (std::is_invocable_r_v<void, MethodType, TranslatorVisitor&, Location, u64>) { 17 if constexpr (std::is_invocable_r_v<void, MethodType, TranslatorVisitor&, Location, u64>) {
18 (visitor.*visitor_method)(pc, insn); 18 (visitor.*method)(pc, insn);
19 } else if constexpr (std::is_invocable_r_v<void, MethodType, TranslatorVisitor&, u64>) { 19 } else if constexpr (std::is_invocable_r_v<void, MethodType, TranslatorVisitor&, u64>) {
20 (visitor.*visitor_method)(insn); 20 (visitor.*method)(insn);
21 } else { 21 } else {
22 (visitor.*visitor_method)(); 22 (visitor.*method)();
23 } 23 }
24} 24}
25 25
diff --git a/src/shader_recompiler/ir_opt/identity_removal_pass.cpp b/src/shader_recompiler/ir_opt/identity_removal_pass.cpp
index 39a972919..593efde39 100644
--- a/src/shader_recompiler/ir_opt/identity_removal_pass.cpp
+++ b/src/shader_recompiler/ir_opt/identity_removal_pass.cpp
@@ -13,7 +13,7 @@ namespace Shader::Optimization {
13void IdentityRemovalPass(IR::Function& function) { 13void IdentityRemovalPass(IR::Function& function) {
14 std::vector<IR::Inst*> to_invalidate; 14 std::vector<IR::Inst*> to_invalidate;
15 15
16 for (auto& block : function.blocks) { 16 for (IR::Block* const block : function.blocks) {
17 for (auto inst = block->begin(); inst != block->end();) { 17 for (auto inst = block->begin(); inst != block->end();) {
18 const size_t num_args{inst->NumArgs()}; 18 const size_t num_args{inst->NumArgs()};
19 for (size_t i = 0; i < num_args; ++i) { 19 for (size_t i = 0; i < num_args; ++i) {
diff --git a/src/shader_recompiler/main.cpp b/src/shader_recompiler/main.cpp
index 19e36590c..9887e066d 100644
--- a/src/shader_recompiler/main.cpp
+++ b/src/shader_recompiler/main.cpp
@@ -6,6 +6,7 @@
6 6
7#include <fmt/format.h> 7#include <fmt/format.h>
8 8
9#include "shader_recompiler/backend/spirv/emit_spirv.h"
9#include "shader_recompiler/file_environment.h" 10#include "shader_recompiler/file_environment.h"
10#include "shader_recompiler/frontend/ir/basic_block.h" 11#include "shader_recompiler/frontend/ir/basic_block.h"
11#include "shader_recompiler/frontend/ir/ir_emitter.h" 12#include "shader_recompiler/frontend/ir/ir_emitter.h"
@@ -51,18 +52,18 @@ void RunDatabase() {
51int main() { 52int main() {
52 // RunDatabase(); 53 // RunDatabase();
53 54
54 // FileEnvironment env{"D:\\Shaders\\Database\\test.bin"};
55 FileEnvironment env{"D:\\Shaders\\Database\\Oninaki\\CS15C2FB1F0B965767.bin"};
56 auto cfg{std::make_unique<Flow::CFG>(env, 0)};
57 // fmt::print(stdout, "{}\n", cfg->Dot());
58
59 auto inst_pool{std::make_unique<ObjectPool<IR::Inst>>()}; 55 auto inst_pool{std::make_unique<ObjectPool<IR::Inst>>()};
60 auto block_pool{std::make_unique<ObjectPool<IR::Block>>()}; 56 auto block_pool{std::make_unique<ObjectPool<IR::Block>>()};
61 57
62 for (int i = 0; i < 8192 * 4; ++i) { 58 // FileEnvironment env{"D:\\Shaders\\Database\\test.bin"};
63 void(inst_pool->Create(IR::Opcode::Void, 0)); 59 FileEnvironment env{"D:\\Shaders\\Database\\Oninaki\\CS15C2FB1F0B965767.bin"};
60 for (int i = 0; i < 1; ++i) {
61 block_pool->ReleaseContents();
62 inst_pool->ReleaseContents();
63 auto cfg{std::make_unique<Flow::CFG>(env, 0)};
64 // fmt::print(stdout, "{}\n", cfg->Dot());
65 IR::Program program{TranslateProgram(*inst_pool, *block_pool, env, *cfg)};
66 // fmt::print(stdout, "{}\n", IR::DumpProgram(program));
67 Backend::SPIRV::EmitSPIRV spirv{program};
64 } 68 }
65
66 IR::Program program{TranslateProgram(*inst_pool, *block_pool, env, *cfg)};
67 fmt::print(stdout, "{}\n", IR::DumpProgram(program));
68} 69}
HIC SVNT DRACONES