summaryrefslogtreecommitdiff
path: root/src/shader_recompiler
diff options
context:
space:
mode:
authorGravatar ReinUsesLisp2021-02-17 00:59:28 -0300
committerGravatar ameerj2021-07-22 21:51:22 -0400
commit85cce78583bc2232428a8fb39e43182877c8d5ad (patch)
tree308f4ef2d145652e08dff1da31c72c2f00dad2e1 /src/shader_recompiler
parentshader: Remove old shader management (diff)
downloadyuzu-85cce78583bc2232428a8fb39e43182877c8d5ad.tar.gz
yuzu-85cce78583bc2232428a8fb39e43182877c8d5ad.tar.xz
yuzu-85cce78583bc2232428a8fb39e43182877c8d5ad.zip
shader: Primitive Vulkan integration
Diffstat (limited to '')
-rw-r--r--src/shader_recompiler/CMakeLists.txt13
-rw-r--r--src/shader_recompiler/backend/spirv/emit_context.cpp2
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.cpp117
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.h419
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp24
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp48
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp42
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp10
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp92
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp60
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp40
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_memory.cpp56
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_select.cpp8
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp10
-rw-r--r--src/shader_recompiler/environment.h6
-rw-r--r--src/shader_recompiler/file_environment.cpp6
-rw-r--r--src/shader_recompiler/file_environment.h4
-rw-r--r--src/shader_recompiler/frontend/ir/basic_block.cpp2
-rw-r--r--src/shader_recompiler/frontend/ir/post_order.cpp2
-rw-r--r--src/shader_recompiler/frontend/maxwell/program.cpp2
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp8
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/impl.h1
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp35
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp4
-rw-r--r--src/shader_recompiler/main.cpp2
-rw-r--r--src/shader_recompiler/profile.h13
-rw-r--r--src/shader_recompiler/recompiler.cpp27
-rw-r--r--src/shader_recompiler/recompiler.h18
28 files changed, 573 insertions, 498 deletions
diff --git a/src/shader_recompiler/CMakeLists.txt b/src/shader_recompiler/CMakeLists.txt
index 84be94a8d..b56bdd3d9 100644
--- a/src/shader_recompiler/CMakeLists.txt
+++ b/src/shader_recompiler/CMakeLists.txt
@@ -1,4 +1,4 @@
1add_executable(shader_recompiler 1add_library(shader_recompiler STATIC
2 backend/spirv/emit_context.cpp 2 backend/spirv/emit_context.cpp
3 backend/spirv/emit_context.h 3 backend/spirv/emit_context.h
4 backend/spirv/emit_spirv.cpp 4 backend/spirv/emit_spirv.cpp
@@ -85,13 +85,19 @@ add_executable(shader_recompiler
85 ir_opt/passes.h 85 ir_opt/passes.h
86 ir_opt/ssa_rewrite_pass.cpp 86 ir_opt/ssa_rewrite_pass.cpp
87 ir_opt/verification_pass.cpp 87 ir_opt/verification_pass.cpp
88 main.cpp
89 object_pool.h 88 object_pool.h
89 profile.h
90 recompiler.cpp
91 recompiler.h
90 shader_info.h 92 shader_info.h
91) 93)
92 94
93target_include_directories(video_core PRIVATE sirit) 95target_include_directories(shader_recompiler PRIVATE sirit)
94target_link_libraries(shader_recompiler PRIVATE fmt::fmt sirit) 96target_link_libraries(shader_recompiler PRIVATE fmt::fmt sirit)
97target_link_libraries(shader_recompiler INTERFACE fmt::fmt sirit)
98
99add_executable(shader_util main.cpp)
100target_link_libraries(shader_util PRIVATE shader_recompiler)
95 101
96if (MSVC) 102if (MSVC)
97 target_compile_options(shader_recompiler PRIVATE 103 target_compile_options(shader_recompiler PRIVATE
@@ -121,3 +127,4 @@ else()
121endif() 127endif()
122 128
123create_target_directory_groups(shader_recompiler) 129create_target_directory_groups(shader_recompiler)
130create_target_directory_groups(shader_util)
diff --git a/src/shader_recompiler/backend/spirv/emit_context.cpp b/src/shader_recompiler/backend/spirv/emit_context.cpp
index 1c985aff8..770067d98 100644
--- a/src/shader_recompiler/backend/spirv/emit_context.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_context.cpp
@@ -115,6 +115,7 @@ void EmitContext::DefineConstantBuffers(const Info& info) {
115 for (const Info::ConstantBufferDescriptor& desc : info.constant_buffer_descriptors) { 115 for (const Info::ConstantBufferDescriptor& desc : info.constant_buffer_descriptors) {
116 const Id id{AddGlobalVariable(uniform_type, spv::StorageClass::Uniform)}; 116 const Id id{AddGlobalVariable(uniform_type, spv::StorageClass::Uniform)};
117 Decorate(id, spv::Decoration::Binding, binding); 117 Decorate(id, spv::Decoration::Binding, binding);
118 Decorate(id, spv::Decoration::DescriptorSet, 0U);
118 Name(id, fmt::format("c{}", desc.index)); 119 Name(id, fmt::format("c{}", desc.index));
119 std::fill_n(cbufs.data() + desc.index, desc.count, id); 120 std::fill_n(cbufs.data() + desc.index, desc.count, id);
120 binding += desc.count; 121 binding += desc.count;
@@ -143,6 +144,7 @@ void EmitContext::DefineStorageBuffers(const Info& info) {
143 for (const Info::StorageBufferDescriptor& desc : info.storage_buffers_descriptors) { 144 for (const Info::StorageBufferDescriptor& desc : info.storage_buffers_descriptors) {
144 const Id id{AddGlobalVariable(storage_type, spv::StorageClass::StorageBuffer)}; 145 const Id id{AddGlobalVariable(storage_type, spv::StorageClass::StorageBuffer)};
145 Decorate(id, spv::Decoration::Binding, binding); 146 Decorate(id, spv::Decoration::Binding, binding);
147 Decorate(id, spv::Decoration::DescriptorSet, 0U);
146 Name(id, fmt::format("ssbo{}", binding)); 148 Name(id, fmt::format("ssbo{}", binding));
147 std::fill_n(ssbos.data() + binding, desc.count, id); 149 std::fill_n(ssbos.data() + binding, desc.count, id);
148 binding += desc.count; 150 binding += desc.count;
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.cpp b/src/shader_recompiler/backend/spirv/emit_spirv.cpp
index 55018332e..d59718435 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.cpp
@@ -2,8 +2,11 @@
2// Licensed under GPLv2 or any later version 2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included. 3// Refer to the license.txt file included.
4 4
5#include <numeric> 5#include <span>
6#include <tuple>
6#include <type_traits> 7#include <type_traits>
8#include <utility>
9#include <vector>
7 10
8#include "shader_recompiler/backend/spirv/emit_spirv.h" 11#include "shader_recompiler/backend/spirv/emit_spirv.h"
9#include "shader_recompiler/frontend/ir/basic_block.h" 12#include "shader_recompiler/frontend/ir/basic_block.h"
@@ -14,10 +17,10 @@
14namespace Shader::Backend::SPIRV { 17namespace Shader::Backend::SPIRV {
15namespace { 18namespace {
16template <class Func> 19template <class Func>
17struct FuncTraits : FuncTraits<decltype(&Func::operator())> {}; 20struct FuncTraits : FuncTraits<Func> {};
18 21
19template <class ClassType, class ReturnType_, class... Args> 22template <class ReturnType_, class... Args>
20struct FuncTraits<ReturnType_ (ClassType::*)(Args...)> { 23struct FuncTraits<ReturnType_ (*)(Args...)> {
21 using ReturnType = ReturnType_; 24 using ReturnType = ReturnType_;
22 25
23 static constexpr size_t NUM_ARGS = sizeof...(Args); 26 static constexpr size_t NUM_ARGS = sizeof...(Args);
@@ -26,15 +29,15 @@ struct FuncTraits<ReturnType_ (ClassType::*)(Args...)> {
26 using ArgType = std::tuple_element_t<I, std::tuple<Args...>>; 29 using ArgType = std::tuple_element_t<I, std::tuple<Args...>>;
27}; 30};
28 31
29template <auto method, typename... Args> 32template <auto func, typename... Args>
30void SetDefinition(EmitSPIRV& emit, EmitContext& ctx, IR::Inst* inst, Args... args) { 33void SetDefinition(EmitContext& ctx, IR::Inst* inst, Args... args) {
31 const Id forward_id{inst->Definition<Id>()}; 34 const Id forward_id{inst->Definition<Id>()};
32 const bool has_forward_id{Sirit::ValidId(forward_id)}; 35 const bool has_forward_id{Sirit::ValidId(forward_id)};
33 Id current_id{}; 36 Id current_id{};
34 if (has_forward_id) { 37 if (has_forward_id) {
35 current_id = ctx.ExchangeCurrentId(forward_id); 38 current_id = ctx.ExchangeCurrentId(forward_id);
36 } 39 }
37 const Id new_id{(emit.*method)(ctx, std::forward<Args>(args)...)}; 40 const Id new_id{func(ctx, std::forward<Args>(args)...)};
38 if (has_forward_id) { 41 if (has_forward_id) {
39 ctx.ExchangeCurrentId(current_id); 42 ctx.ExchangeCurrentId(current_id);
40 } else { 43 } else {
@@ -55,42 +58,62 @@ ArgType Arg(EmitContext& ctx, const IR::Value& arg) {
55 } 58 }
56} 59}
57 60
58template <auto method, bool is_first_arg_inst, size_t... I> 61template <auto func, bool is_first_arg_inst, size_t... I>
59void Invoke(EmitSPIRV& emit, EmitContext& ctx, IR::Inst* inst, std::index_sequence<I...>) { 62void Invoke(EmitContext& ctx, IR::Inst* inst, std::index_sequence<I...>) {
60 using Traits = FuncTraits<decltype(method)>; 63 using Traits = FuncTraits<decltype(func)>;
61 if constexpr (std::is_same_v<Traits::ReturnType, Id>) { 64 if constexpr (std::is_same_v<Traits::ReturnType, Id>) {
62 if constexpr (is_first_arg_inst) { 65 if constexpr (is_first_arg_inst) {
63 SetDefinition<method>(emit, ctx, inst, inst, 66 SetDefinition<func>(ctx, inst, inst, Arg<Traits::ArgType<I + 2>>(ctx, inst->Arg(I))...);
64 Arg<Traits::ArgType<I + 2>>(ctx, inst->Arg(I))...);
65 } else { 67 } else {
66 SetDefinition<method>(emit, ctx, inst, 68 SetDefinition<func>(ctx, inst, Arg<Traits::ArgType<I + 1>>(ctx, inst->Arg(I))...);
67 Arg<Traits::ArgType<I + 1>>(ctx, inst->Arg(I))...);
68 } 69 }
69 } else { 70 } else {
70 if constexpr (is_first_arg_inst) { 71 if constexpr (is_first_arg_inst) {
71 (emit.*method)(ctx, inst, Arg<Traits::ArgType<I + 2>>(ctx, inst->Arg(I))...); 72 func(ctx, inst, Arg<Traits::ArgType<I + 2>>(ctx, inst->Arg(I))...);
72 } else { 73 } else {
73 (emit.*method)(ctx, Arg<Traits::ArgType<I + 1>>(ctx, inst->Arg(I))...); 74 func(ctx, Arg<Traits::ArgType<I + 1>>(ctx, inst->Arg(I))...);
74 } 75 }
75 } 76 }
76} 77}
77 78
78template <auto method> 79template <auto func>
79void Invoke(EmitSPIRV& emit, EmitContext& ctx, IR::Inst* inst) { 80void Invoke(EmitContext& ctx, IR::Inst* inst) {
80 using Traits = FuncTraits<decltype(method)>; 81 using Traits = FuncTraits<decltype(func)>;
81 static_assert(Traits::NUM_ARGS >= 1, "Insufficient arguments"); 82 static_assert(Traits::NUM_ARGS >= 1, "Insufficient arguments");
82 if constexpr (Traits::NUM_ARGS == 1) { 83 if constexpr (Traits::NUM_ARGS == 1) {
83 Invoke<method, false>(emit, ctx, inst, std::make_index_sequence<0>{}); 84 Invoke<func, false>(ctx, inst, std::make_index_sequence<0>{});
84 } else { 85 } else {
85 using FirstArgType = typename Traits::template ArgType<1>; 86 using FirstArgType = typename Traits::template ArgType<1>;
86 static constexpr bool is_first_arg_inst = std::is_same_v<FirstArgType, IR::Inst*>; 87 static constexpr bool is_first_arg_inst = std::is_same_v<FirstArgType, IR::Inst*>;
87 using Indices = std::make_index_sequence<Traits::NUM_ARGS - (is_first_arg_inst ? 2 : 1)>; 88 using Indices = std::make_index_sequence<Traits::NUM_ARGS - (is_first_arg_inst ? 2 : 1)>;
88 Invoke<method, is_first_arg_inst>(emit, ctx, inst, Indices{}); 89 Invoke<func, is_first_arg_inst>(ctx, inst, Indices{});
90 }
91}
92
93void EmitInst(EmitContext& ctx, IR::Inst* inst) {
94 switch (inst->Opcode()) {
95#define OPCODE(name, result_type, ...) \
96 case IR::Opcode::name: \
97 return Invoke<&Emit##name>(ctx, inst);
98#include "shader_recompiler/frontend/ir/opcodes.inc"
99#undef OPCODE
100 }
101 throw LogicError("Invalid opcode {}", inst->Opcode());
102}
103
104Id TypeId(const EmitContext& ctx, IR::Type type) {
105 switch (type) {
106 case IR::Type::U1:
107 return ctx.U1;
108 case IR::Type::U32:
109 return ctx.U32[1];
110 default:
111 throw NotImplementedException("Phi node type {}", type);
89 } 112 }
90} 113}
91} // Anonymous namespace 114} // Anonymous namespace
92 115
93EmitSPIRV::EmitSPIRV(IR::Program& program) { 116std::vector<u32> EmitSPIRV(Environment& env, IR::Program& program) {
94 EmitContext ctx{program}; 117 EmitContext ctx{program};
95 const Id void_function{ctx.TypeFunction(ctx.void_id)}; 118 const Id void_function{ctx.TypeFunction(ctx.void_id)};
96 // FIXME: Forward declare functions (needs sirit support) 119 // FIXME: Forward declare functions (needs sirit support)
@@ -112,43 +135,17 @@ EmitSPIRV::EmitSPIRV(IR::Program& program) {
112 if (program.info.uses_local_invocation_id) { 135 if (program.info.uses_local_invocation_id) {
113 interfaces.push_back(ctx.local_invocation_id); 136 interfaces.push_back(ctx.local_invocation_id);
114 } 137 }
115
116 const std::span interfaces_span(interfaces.data(), interfaces.size()); 138 const std::span interfaces_span(interfaces.data(), interfaces.size());
117 ctx.AddEntryPoint(spv::ExecutionModel::Fragment, func, "main", interfaces_span); 139 ctx.AddEntryPoint(spv::ExecutionModel::GLCompute, func, "main", interfaces_span);
118 ctx.AddExecutionMode(func, spv::ExecutionMode::OriginUpperLeft);
119
120 std::vector<u32> result{ctx.Assemble()};
121 std::FILE* file{std::fopen("D:\\shader.spv", "wb")};
122 std::fwrite(result.data(), sizeof(u32), result.size(), file);
123 std::fclose(file);
124 std::system("spirv-dis D:\\shader.spv") == 0 &&
125 std::system("spirv-val --uniform-buffer-standard-layout D:\\shader.spv") == 0 &&
126 std::system("spirv-cross -V D:\\shader.spv") == 0;
127}
128 140
129void EmitSPIRV::EmitInst(EmitContext& ctx, IR::Inst* inst) { 141 const std::array<u32, 3> workgroup_size{env.WorkgroupSize()};
130 switch (inst->Opcode()) { 142 ctx.AddExecutionMode(func, spv::ExecutionMode::LocalSize, workgroup_size[0], workgroup_size[1],
131#define OPCODE(name, result_type, ...) \ 143 workgroup_size[2]);
132 case IR::Opcode::name: \
133 return Invoke<&EmitSPIRV::Emit##name>(*this, ctx, inst);
134#include "shader_recompiler/frontend/ir/opcodes.inc"
135#undef OPCODE
136 }
137 throw LogicError("Invalid opcode {}", inst->Opcode());
138}
139 144
140static Id TypeId(const EmitContext& ctx, IR::Type type) { 145 return ctx.Assemble();
141 switch (type) {
142 case IR::Type::U1:
143 return ctx.U1;
144 case IR::Type::U32:
145 return ctx.U32[1];
146 default:
147 throw NotImplementedException("Phi node type {}", type);
148 }
149} 146}
150 147
151Id EmitSPIRV::EmitPhi(EmitContext& ctx, IR::Inst* inst) { 148Id EmitPhi(EmitContext& ctx, IR::Inst* inst) {
152 const size_t num_args{inst->NumArgs()}; 149 const size_t num_args{inst->NumArgs()};
153 boost::container::small_vector<Id, 32> operands; 150 boost::container::small_vector<Id, 32> operands;
154 operands.reserve(num_args * 2); 151 operands.reserve(num_args * 2);
@@ -178,25 +175,25 @@ Id EmitSPIRV::EmitPhi(EmitContext& ctx, IR::Inst* inst) {
178 return ctx.OpPhi(result_type, std::span(operands.data(), operands.size())); 175 return ctx.OpPhi(result_type, std::span(operands.data(), operands.size()));
179} 176}
180 177
181void EmitSPIRV::EmitVoid(EmitContext&) {} 178void EmitVoid(EmitContext&) {}
182 179
183Id EmitSPIRV::EmitIdentity(EmitContext& ctx, const IR::Value& value) { 180Id EmitIdentity(EmitContext& ctx, const IR::Value& value) {
184 return ctx.Def(value); 181 return ctx.Def(value);
185} 182}
186 183
187void EmitSPIRV::EmitGetZeroFromOp(EmitContext&) { 184void EmitGetZeroFromOp(EmitContext&) {
188 throw LogicError("Unreachable instruction"); 185 throw LogicError("Unreachable instruction");
189} 186}
190 187
191void EmitSPIRV::EmitGetSignFromOp(EmitContext&) { 188void EmitGetSignFromOp(EmitContext&) {
192 throw LogicError("Unreachable instruction"); 189 throw LogicError("Unreachable instruction");
193} 190}
194 191
195void EmitSPIRV::EmitGetCarryFromOp(EmitContext&) { 192void EmitGetCarryFromOp(EmitContext&) {
196 throw LogicError("Unreachable instruction"); 193 throw LogicError("Unreachable instruction");
197} 194}
198 195
199void EmitSPIRV::EmitGetOverflowFromOp(EmitContext&) { 196void EmitGetOverflowFromOp(EmitContext&) {
200 throw LogicError("Unreachable instruction"); 197 throw LogicError("Unreachable instruction");
201} 198}
202 199
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index 8bde82613..5813f51ff 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -8,223 +8,218 @@
8 8
9#include "common/common_types.h" 9#include "common/common_types.h"
10#include "shader_recompiler/backend/spirv/emit_context.h" 10#include "shader_recompiler/backend/spirv/emit_context.h"
11#include "shader_recompiler/environment.h"
11#include "shader_recompiler/frontend/ir/microinstruction.h" 12#include "shader_recompiler/frontend/ir/microinstruction.h"
12#include "shader_recompiler/frontend/ir/program.h" 13#include "shader_recompiler/frontend/ir/program.h"
13 14
14namespace Shader::Backend::SPIRV { 15namespace Shader::Backend::SPIRV {
15 16
16class EmitSPIRV { 17[[nodiscard]] std::vector<u32> EmitSPIRV(Environment& env, IR::Program& program);
17public:
18 explicit EmitSPIRV(IR::Program& program);
19 18
20private: 19// Microinstruction emitters
21 void EmitInst(EmitContext& ctx, IR::Inst* inst); 20Id EmitPhi(EmitContext& ctx, IR::Inst* inst);
22 21void EmitVoid(EmitContext& ctx);
23 // Microinstruction emitters 22Id EmitIdentity(EmitContext& ctx, const IR::Value& value);
24 Id EmitPhi(EmitContext& ctx, IR::Inst* inst); 23void EmitBranch(EmitContext& ctx, IR::Block* label);
25 void EmitVoid(EmitContext& ctx); 24void EmitBranchConditional(EmitContext& ctx, Id condition, IR::Block* true_label,
26 Id EmitIdentity(EmitContext& ctx, const IR::Value& value); 25 IR::Block* false_label);
27 void EmitBranch(EmitContext& ctx, IR::Block* label); 26void EmitLoopMerge(EmitContext& ctx, IR::Block* merge_label, IR::Block* continue_label);
28 void EmitBranchConditional(EmitContext& ctx, Id condition, IR::Block* true_label, 27void EmitSelectionMerge(EmitContext& ctx, IR::Block* merge_label);
29 IR::Block* false_label); 28void EmitReturn(EmitContext& ctx);
30 void EmitLoopMerge(EmitContext& ctx, IR::Block* merge_label, IR::Block* continue_label); 29void EmitGetRegister(EmitContext& ctx);
31 void EmitSelectionMerge(EmitContext& ctx, IR::Block* merge_label); 30void EmitSetRegister(EmitContext& ctx);
32 void EmitReturn(EmitContext& ctx); 31void EmitGetPred(EmitContext& ctx);
33 void EmitGetRegister(EmitContext& ctx); 32void EmitSetPred(EmitContext& ctx);
34 void EmitSetRegister(EmitContext& ctx); 33void EmitSetGotoVariable(EmitContext& ctx);
35 void EmitGetPred(EmitContext& ctx); 34void EmitGetGotoVariable(EmitContext& ctx);
36 void EmitSetPred(EmitContext& ctx); 35Id EmitGetCbuf(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
37 void EmitSetGotoVariable(EmitContext& ctx); 36void EmitGetAttribute(EmitContext& ctx);
38 void EmitGetGotoVariable(EmitContext& ctx); 37void EmitSetAttribute(EmitContext& ctx);
39 Id EmitGetCbuf(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset); 38void EmitGetAttributeIndexed(EmitContext& ctx);
40 void EmitGetAttribute(EmitContext& ctx); 39void EmitSetAttributeIndexed(EmitContext& ctx);
41 void EmitSetAttribute(EmitContext& ctx); 40void EmitGetZFlag(EmitContext& ctx);
42 void EmitGetAttributeIndexed(EmitContext& ctx); 41void EmitGetSFlag(EmitContext& ctx);
43 void EmitSetAttributeIndexed(EmitContext& ctx); 42void EmitGetCFlag(EmitContext& ctx);
44 void EmitGetZFlag(EmitContext& ctx); 43void EmitGetOFlag(EmitContext& ctx);
45 void EmitGetSFlag(EmitContext& ctx); 44void EmitSetZFlag(EmitContext& ctx);
46 void EmitGetCFlag(EmitContext& ctx); 45void EmitSetSFlag(EmitContext& ctx);
47 void EmitGetOFlag(EmitContext& ctx); 46void EmitSetCFlag(EmitContext& ctx);
48 void EmitSetZFlag(EmitContext& ctx); 47void EmitSetOFlag(EmitContext& ctx);
49 void EmitSetSFlag(EmitContext& ctx); 48Id EmitWorkgroupId(EmitContext& ctx);
50 void EmitSetCFlag(EmitContext& ctx); 49Id EmitLocalInvocationId(EmitContext& ctx);
51 void EmitSetOFlag(EmitContext& ctx); 50Id EmitUndefU1(EmitContext& ctx);
52 Id EmitWorkgroupId(EmitContext& ctx); 51Id EmitUndefU8(EmitContext& ctx);
53 Id EmitLocalInvocationId(EmitContext& ctx); 52Id EmitUndefU16(EmitContext& ctx);
54 Id EmitUndefU1(EmitContext& ctx); 53Id EmitUndefU32(EmitContext& ctx);
55 Id EmitUndefU8(EmitContext& ctx); 54Id EmitUndefU64(EmitContext& ctx);
56 Id EmitUndefU16(EmitContext& ctx); 55void EmitLoadGlobalU8(EmitContext& ctx);
57 Id EmitUndefU32(EmitContext& ctx); 56void EmitLoadGlobalS8(EmitContext& ctx);
58 Id EmitUndefU64(EmitContext& ctx); 57void EmitLoadGlobalU16(EmitContext& ctx);
59 void EmitLoadGlobalU8(EmitContext& ctx); 58void EmitLoadGlobalS16(EmitContext& ctx);
60 void EmitLoadGlobalS8(EmitContext& ctx); 59void EmitLoadGlobal32(EmitContext& ctx);
61 void EmitLoadGlobalU16(EmitContext& ctx); 60void EmitLoadGlobal64(EmitContext& ctx);
62 void EmitLoadGlobalS16(EmitContext& ctx); 61void EmitLoadGlobal128(EmitContext& ctx);
63 void EmitLoadGlobal32(EmitContext& ctx); 62void EmitWriteGlobalU8(EmitContext& ctx);
64 void EmitLoadGlobal64(EmitContext& ctx); 63void EmitWriteGlobalS8(EmitContext& ctx);
65 void EmitLoadGlobal128(EmitContext& ctx); 64void EmitWriteGlobalU16(EmitContext& ctx);
66 void EmitWriteGlobalU8(EmitContext& ctx); 65void EmitWriteGlobalS16(EmitContext& ctx);
67 void EmitWriteGlobalS8(EmitContext& ctx); 66void EmitWriteGlobal32(EmitContext& ctx);
68 void EmitWriteGlobalU16(EmitContext& ctx); 67void EmitWriteGlobal64(EmitContext& ctx);
69 void EmitWriteGlobalS16(EmitContext& ctx); 68void EmitWriteGlobal128(EmitContext& ctx);
70 void EmitWriteGlobal32(EmitContext& ctx); 69void EmitLoadStorageU8(EmitContext& ctx);
71 void EmitWriteGlobal64(EmitContext& ctx); 70void EmitLoadStorageS8(EmitContext& ctx);
72 void EmitWriteGlobal128(EmitContext& ctx); 71void EmitLoadStorageU16(EmitContext& ctx);
73 void EmitLoadStorageU8(EmitContext& ctx); 72void EmitLoadStorageS16(EmitContext& ctx);
74 void EmitLoadStorageS8(EmitContext& ctx); 73Id EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset);
75 void EmitLoadStorageU16(EmitContext& ctx); 74void EmitLoadStorage64(EmitContext& ctx);
76 void EmitLoadStorageS16(EmitContext& ctx); 75void EmitLoadStorage128(EmitContext& ctx);
77 Id EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset); 76void EmitWriteStorageU8(EmitContext& ctx);
78 void EmitLoadStorage64(EmitContext& ctx); 77void EmitWriteStorageS8(EmitContext& ctx);
79 void EmitLoadStorage128(EmitContext& ctx); 78void EmitWriteStorageU16(EmitContext& ctx);
80 void EmitWriteStorageU8(EmitContext& ctx); 79void EmitWriteStorageS16(EmitContext& ctx);
81 void EmitWriteStorageS8(EmitContext& ctx); 80void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset,
82 void EmitWriteStorageU16(EmitContext& ctx); 81 Id value);
83 void EmitWriteStorageS16(EmitContext& ctx); 82void EmitWriteStorage64(EmitContext& ctx);
84 void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset, 83void EmitWriteStorage128(EmitContext& ctx);
85 Id value); 84void EmitCompositeConstructU32x2(EmitContext& ctx);
86 void EmitWriteStorage64(EmitContext& ctx); 85void EmitCompositeConstructU32x3(EmitContext& ctx);
87 void EmitWriteStorage128(EmitContext& ctx); 86void EmitCompositeConstructU32x4(EmitContext& ctx);
88 void EmitCompositeConstructU32x2(EmitContext& ctx); 87void EmitCompositeExtractU32x2(EmitContext& ctx);
89 void EmitCompositeConstructU32x3(EmitContext& ctx); 88Id EmitCompositeExtractU32x3(EmitContext& ctx, Id vector, u32 index);
90 void EmitCompositeConstructU32x4(EmitContext& ctx); 89void EmitCompositeExtractU32x4(EmitContext& ctx);
91 void EmitCompositeExtractU32x2(EmitContext& ctx); 90void EmitCompositeConstructF16x2(EmitContext& ctx);
92 Id EmitCompositeExtractU32x3(EmitContext& ctx, Id vector, u32 index); 91void EmitCompositeConstructF16x3(EmitContext& ctx);
93 void EmitCompositeExtractU32x4(EmitContext& ctx); 92void EmitCompositeConstructF16x4(EmitContext& ctx);
94 void EmitCompositeConstructF16x2(EmitContext& ctx); 93void EmitCompositeExtractF16x2(EmitContext& ctx);
95 void EmitCompositeConstructF16x3(EmitContext& ctx); 94void EmitCompositeExtractF16x3(EmitContext& ctx);
96 void EmitCompositeConstructF16x4(EmitContext& ctx); 95void EmitCompositeExtractF16x4(EmitContext& ctx);
97 void EmitCompositeExtractF16x2(EmitContext& ctx); 96void EmitCompositeConstructF32x2(EmitContext& ctx);
98 void EmitCompositeExtractF16x3(EmitContext& ctx); 97void EmitCompositeConstructF32x3(EmitContext& ctx);
99 void EmitCompositeExtractF16x4(EmitContext& ctx); 98void EmitCompositeConstructF32x4(EmitContext& ctx);
100 void EmitCompositeConstructF32x2(EmitContext& ctx); 99void EmitCompositeExtractF32x2(EmitContext& ctx);
101 void EmitCompositeConstructF32x3(EmitContext& ctx); 100void EmitCompositeExtractF32x3(EmitContext& ctx);
102 void EmitCompositeConstructF32x4(EmitContext& ctx); 101void EmitCompositeExtractF32x4(EmitContext& ctx);
103 void EmitCompositeExtractF32x2(EmitContext& ctx); 102void EmitCompositeConstructF64x2(EmitContext& ctx);
104 void EmitCompositeExtractF32x3(EmitContext& ctx); 103void EmitCompositeConstructF64x3(EmitContext& ctx);
105 void EmitCompositeExtractF32x4(EmitContext& ctx); 104void EmitCompositeConstructF64x4(EmitContext& ctx);
106 void EmitCompositeConstructF64x2(EmitContext& ctx); 105void EmitCompositeExtractF64x2(EmitContext& ctx);
107 void EmitCompositeConstructF64x3(EmitContext& ctx); 106void EmitCompositeExtractF64x3(EmitContext& ctx);
108 void EmitCompositeConstructF64x4(EmitContext& ctx); 107void EmitCompositeExtractF64x4(EmitContext& ctx);
109 void EmitCompositeExtractF64x2(EmitContext& ctx); 108void EmitSelect8(EmitContext& ctx);
110 void EmitCompositeExtractF64x3(EmitContext& ctx); 109void EmitSelect16(EmitContext& ctx);
111 void EmitCompositeExtractF64x4(EmitContext& ctx); 110void EmitSelect32(EmitContext& ctx);
112 void EmitSelect8(EmitContext& ctx); 111void EmitSelect64(EmitContext& ctx);
113 void EmitSelect16(EmitContext& ctx); 112void EmitBitCastU16F16(EmitContext& ctx);
114 void EmitSelect32(EmitContext& ctx); 113Id EmitBitCastU32F32(EmitContext& ctx, Id value);
115 void EmitSelect64(EmitContext& ctx); 114void EmitBitCastU64F64(EmitContext& ctx);
116 void EmitBitCastU16F16(EmitContext& ctx); 115void EmitBitCastF16U16(EmitContext& ctx);
117 Id EmitBitCastU32F32(EmitContext& ctx, Id value); 116Id EmitBitCastF32U32(EmitContext& ctx, Id value);
118 void EmitBitCastU64F64(EmitContext& ctx); 117void EmitBitCastF64U64(EmitContext& ctx);
119 void EmitBitCastF16U16(EmitContext& ctx); 118void EmitPackUint2x32(EmitContext& ctx);
120 Id EmitBitCastF32U32(EmitContext& ctx, Id value); 119void EmitUnpackUint2x32(EmitContext& ctx);
121 void EmitBitCastF64U64(EmitContext& ctx); 120void EmitPackFloat2x16(EmitContext& ctx);
122 void EmitPackUint2x32(EmitContext& ctx); 121void EmitUnpackFloat2x16(EmitContext& ctx);
123 void EmitUnpackUint2x32(EmitContext& ctx); 122void EmitPackDouble2x32(EmitContext& ctx);
124 void EmitPackFloat2x16(EmitContext& ctx); 123void EmitUnpackDouble2x32(EmitContext& ctx);
125 void EmitUnpackFloat2x16(EmitContext& ctx); 124void EmitGetZeroFromOp(EmitContext& ctx);
126 void EmitPackDouble2x32(EmitContext& ctx); 125void EmitGetSignFromOp(EmitContext& ctx);
127 void EmitUnpackDouble2x32(EmitContext& ctx); 126void EmitGetCarryFromOp(EmitContext& ctx);
128 void EmitGetZeroFromOp(EmitContext& ctx); 127void EmitGetOverflowFromOp(EmitContext& ctx);
129 void EmitGetSignFromOp(EmitContext& ctx); 128void EmitFPAbs16(EmitContext& ctx);
130 void EmitGetCarryFromOp(EmitContext& ctx); 129void EmitFPAbs32(EmitContext& ctx);
131 void EmitGetOverflowFromOp(EmitContext& ctx); 130void EmitFPAbs64(EmitContext& ctx);
132 void EmitFPAbs16(EmitContext& ctx); 131Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
133 void EmitFPAbs32(EmitContext& ctx); 132Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
134 void EmitFPAbs64(EmitContext& ctx); 133Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
135 Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b); 134Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
136 Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); 135Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
137 Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b); 136Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c);
138 Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c); 137void EmitFPMax32(EmitContext& ctx);
139 Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c); 138void EmitFPMax64(EmitContext& ctx);
140 Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c); 139void EmitFPMin32(EmitContext& ctx);
141 void EmitFPMax32(EmitContext& ctx); 140void EmitFPMin64(EmitContext& ctx);
142 void EmitFPMax64(EmitContext& ctx); 141Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
143 void EmitFPMin32(EmitContext& ctx); 142Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
144 void EmitFPMin64(EmitContext& ctx); 143Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
145 Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b); 144void EmitFPNeg16(EmitContext& ctx);
146 Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); 145void EmitFPNeg32(EmitContext& ctx);
147 Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b); 146void EmitFPNeg64(EmitContext& ctx);
148 void EmitFPNeg16(EmitContext& ctx); 147void EmitFPRecip32(EmitContext& ctx);
149 void EmitFPNeg32(EmitContext& ctx); 148void EmitFPRecip64(EmitContext& ctx);
150 void EmitFPNeg64(EmitContext& ctx); 149void EmitFPRecipSqrt32(EmitContext& ctx);
151 void EmitFPRecip32(EmitContext& ctx); 150void EmitFPRecipSqrt64(EmitContext& ctx);
152 void EmitFPRecip64(EmitContext& ctx); 151void EmitFPSqrt(EmitContext& ctx);
153 void EmitFPRecipSqrt32(EmitContext& ctx); 152void EmitFPSin(EmitContext& ctx);
154 void EmitFPRecipSqrt64(EmitContext& ctx); 153void EmitFPSinNotReduced(EmitContext& ctx);
155 void EmitFPSqrt(EmitContext& ctx); 154void EmitFPExp2(EmitContext& ctx);
156 void EmitFPSin(EmitContext& ctx); 155void EmitFPExp2NotReduced(EmitContext& ctx);
157 void EmitFPSinNotReduced(EmitContext& ctx); 156void EmitFPCos(EmitContext& ctx);
158 void EmitFPExp2(EmitContext& ctx); 157void EmitFPCosNotReduced(EmitContext& ctx);
159 void EmitFPExp2NotReduced(EmitContext& ctx); 158void EmitFPLog2(EmitContext& ctx);
160 void EmitFPCos(EmitContext& ctx); 159void EmitFPSaturate16(EmitContext& ctx);
161 void EmitFPCosNotReduced(EmitContext& ctx); 160void EmitFPSaturate32(EmitContext& ctx);
162 void EmitFPLog2(EmitContext& ctx); 161void EmitFPSaturate64(EmitContext& ctx);
163 void EmitFPSaturate16(EmitContext& ctx); 162void EmitFPRoundEven16(EmitContext& ctx);
164 void EmitFPSaturate32(EmitContext& ctx); 163void EmitFPRoundEven32(EmitContext& ctx);
165 void EmitFPSaturate64(EmitContext& ctx); 164void EmitFPRoundEven64(EmitContext& ctx);
166 void EmitFPRoundEven16(EmitContext& ctx); 165void EmitFPFloor16(EmitContext& ctx);
167 void EmitFPRoundEven32(EmitContext& ctx); 166void EmitFPFloor32(EmitContext& ctx);
168 void EmitFPRoundEven64(EmitContext& ctx); 167void EmitFPFloor64(EmitContext& ctx);
169 void EmitFPFloor16(EmitContext& ctx); 168void EmitFPCeil16(EmitContext& ctx);
170 void EmitFPFloor32(EmitContext& ctx); 169void EmitFPCeil32(EmitContext& ctx);
171 void EmitFPFloor64(EmitContext& ctx); 170void EmitFPCeil64(EmitContext& ctx);
172 void EmitFPCeil16(EmitContext& ctx); 171void EmitFPTrunc16(EmitContext& ctx);
173 void EmitFPCeil32(EmitContext& ctx); 172void EmitFPTrunc32(EmitContext& ctx);
174 void EmitFPCeil64(EmitContext& ctx); 173void EmitFPTrunc64(EmitContext& ctx);
175 void EmitFPTrunc16(EmitContext& ctx); 174Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b);
176 void EmitFPTrunc32(EmitContext& ctx); 175void EmitIAdd64(EmitContext& ctx);
177 void EmitFPTrunc64(EmitContext& ctx); 176Id EmitISub32(EmitContext& ctx, Id a, Id b);
178 Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b); 177void EmitISub64(EmitContext& ctx);
179 void EmitIAdd64(EmitContext& ctx); 178Id EmitIMul32(EmitContext& ctx, Id a, Id b);
180 Id EmitISub32(EmitContext& ctx, Id a, Id b); 179void EmitINeg32(EmitContext& ctx);
181 void EmitISub64(EmitContext& ctx); 180void EmitIAbs32(EmitContext& ctx);
182 Id EmitIMul32(EmitContext& ctx, Id a, Id b); 181Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
183 void EmitINeg32(EmitContext& ctx); 182void EmitShiftRightLogical32(EmitContext& ctx);
184 void EmitIAbs32(EmitContext& ctx); 183void EmitShiftRightArithmetic32(EmitContext& ctx);
185 Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift); 184void EmitBitwiseAnd32(EmitContext& ctx);
186 void EmitShiftRightLogical32(EmitContext& ctx); 185void EmitBitwiseOr32(EmitContext& ctx);
187 void EmitShiftRightArithmetic32(EmitContext& ctx); 186void EmitBitwiseXor32(EmitContext& ctx);
188 void EmitBitwiseAnd32(EmitContext& ctx); 187void EmitBitFieldInsert(EmitContext& ctx);
189 void EmitBitwiseOr32(EmitContext& ctx); 188void EmitBitFieldSExtract(EmitContext& ctx);
190 void EmitBitwiseXor32(EmitContext& ctx); 189Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
191 void EmitBitFieldInsert(EmitContext& ctx); 190Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
192 void EmitBitFieldSExtract(EmitContext& ctx); 191void EmitULessThan(EmitContext& ctx);
193 Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count); 192void EmitIEqual(EmitContext& ctx);
194 Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs); 193void EmitSLessThanEqual(EmitContext& ctx);
195 void EmitULessThan(EmitContext& ctx); 194void EmitULessThanEqual(EmitContext& ctx);
196 void EmitIEqual(EmitContext& ctx); 195Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
197 void EmitSLessThanEqual(EmitContext& ctx); 196void EmitUGreaterThan(EmitContext& ctx);
198 void EmitULessThanEqual(EmitContext& ctx); 197void EmitINotEqual(EmitContext& ctx);
199 Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs); 198void EmitSGreaterThanEqual(EmitContext& ctx);
200 void EmitUGreaterThan(EmitContext& ctx); 199Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs);
201 void EmitINotEqual(EmitContext& ctx); 200void EmitLogicalOr(EmitContext& ctx);
202 void EmitSGreaterThanEqual(EmitContext& ctx); 201void EmitLogicalAnd(EmitContext& ctx);
203 Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs); 202void EmitLogicalXor(EmitContext& ctx);
204 void EmitLogicalOr(EmitContext& ctx); 203void EmitLogicalNot(EmitContext& ctx);
205 void EmitLogicalAnd(EmitContext& ctx); 204void EmitConvertS16F16(EmitContext& ctx);
206 void EmitLogicalXor(EmitContext& ctx); 205void EmitConvertS16F32(EmitContext& ctx);
207 void EmitLogicalNot(EmitContext& ctx); 206void EmitConvertS16F64(EmitContext& ctx);
208 void EmitConvertS16F16(EmitContext& ctx); 207void EmitConvertS32F16(EmitContext& ctx);
209 void EmitConvertS16F32(EmitContext& ctx); 208void EmitConvertS32F32(EmitContext& ctx);
210 void EmitConvertS16F64(EmitContext& ctx); 209void EmitConvertS32F64(EmitContext& ctx);
211 void EmitConvertS32F16(EmitContext& ctx); 210void EmitConvertS64F16(EmitContext& ctx);
212 void EmitConvertS32F32(EmitContext& ctx); 211void EmitConvertS64F32(EmitContext& ctx);
213 void EmitConvertS32F64(EmitContext& ctx); 212void EmitConvertS64F64(EmitContext& ctx);
214 void EmitConvertS64F16(EmitContext& ctx); 213void EmitConvertU16F16(EmitContext& ctx);
215 void EmitConvertS64F32(EmitContext& ctx); 214void EmitConvertU16F32(EmitContext& ctx);
216 void EmitConvertS64F64(EmitContext& ctx); 215void EmitConvertU16F64(EmitContext& ctx);
217 void EmitConvertU16F16(EmitContext& ctx); 216void EmitConvertU32F16(EmitContext& ctx);
218 void EmitConvertU16F32(EmitContext& ctx); 217void EmitConvertU32F32(EmitContext& ctx);
219 void EmitConvertU16F64(EmitContext& ctx); 218void EmitConvertU32F64(EmitContext& ctx);
220 void EmitConvertU32F16(EmitContext& ctx); 219void EmitConvertU64F16(EmitContext& ctx);
221 void EmitConvertU32F32(EmitContext& ctx); 220void EmitConvertU64F32(EmitContext& ctx);
222 void EmitConvertU32F64(EmitContext& ctx); 221void EmitConvertU64F64(EmitContext& ctx);
223 void EmitConvertU64F16(EmitContext& ctx); 222void EmitConvertU64U32(EmitContext& ctx);
224 void EmitConvertU64F32(EmitContext& ctx); 223void EmitConvertU32U64(EmitContext& ctx);
225 void EmitConvertU64F64(EmitContext& ctx);
226 void EmitConvertU64U32(EmitContext& ctx);
227 void EmitConvertU32U64(EmitContext& ctx);
228};
229 224
230} // namespace Shader::Backend::SPIRV 225} // namespace Shader::Backend::SPIRV
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp
index af82df99c..49c200498 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_bitwise_conversion.cpp
@@ -6,51 +6,51 @@
6 6
7namespace Shader::Backend::SPIRV { 7namespace Shader::Backend::SPIRV {
8 8
9void EmitSPIRV::EmitBitCastU16F16(EmitContext&) { 9void EmitBitCastU16F16(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction"); 10 throw NotImplementedException("SPIR-V Instruction");
11} 11}
12 12
13Id EmitSPIRV::EmitBitCastU32F32(EmitContext& ctx, Id value) { 13Id EmitBitCastU32F32(EmitContext& ctx, Id value) {
14 return ctx.OpBitcast(ctx.U32[1], value); 14 return ctx.OpBitcast(ctx.U32[1], value);
15} 15}
16 16
17void EmitSPIRV::EmitBitCastU64F64(EmitContext&) { 17void EmitBitCastU64F64(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction"); 18 throw NotImplementedException("SPIR-V Instruction");
19} 19}
20 20
21void EmitSPIRV::EmitBitCastF16U16(EmitContext&) { 21void EmitBitCastF16U16(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction"); 22 throw NotImplementedException("SPIR-V Instruction");
23} 23}
24 24
25Id EmitSPIRV::EmitBitCastF32U32(EmitContext& ctx, Id value) { 25Id EmitBitCastF32U32(EmitContext& ctx, Id value) {
26 return ctx.OpBitcast(ctx.F32[1], value); 26 return ctx.OpBitcast(ctx.F32[1], value);
27} 27}
28 28
29void EmitSPIRV::EmitBitCastF64U64(EmitContext&) { 29void EmitBitCastF64U64(EmitContext&) {
30 throw NotImplementedException("SPIR-V Instruction"); 30 throw NotImplementedException("SPIR-V Instruction");
31} 31}
32 32
33void EmitSPIRV::EmitPackUint2x32(EmitContext&) { 33void EmitPackUint2x32(EmitContext&) {
34 throw NotImplementedException("SPIR-V Instruction"); 34 throw NotImplementedException("SPIR-V Instruction");
35} 35}
36 36
37void EmitSPIRV::EmitUnpackUint2x32(EmitContext&) { 37void EmitUnpackUint2x32(EmitContext&) {
38 throw NotImplementedException("SPIR-V Instruction"); 38 throw NotImplementedException("SPIR-V Instruction");
39} 39}
40 40
41void EmitSPIRV::EmitPackFloat2x16(EmitContext&) { 41void EmitPackFloat2x16(EmitContext&) {
42 throw NotImplementedException("SPIR-V Instruction"); 42 throw NotImplementedException("SPIR-V Instruction");
43} 43}
44 44
45void EmitSPIRV::EmitUnpackFloat2x16(EmitContext&) { 45void EmitUnpackFloat2x16(EmitContext&) {
46 throw NotImplementedException("SPIR-V Instruction"); 46 throw NotImplementedException("SPIR-V Instruction");
47} 47}
48 48
49void EmitSPIRV::EmitPackDouble2x32(EmitContext&) { 49void EmitPackDouble2x32(EmitContext&) {
50 throw NotImplementedException("SPIR-V Instruction"); 50 throw NotImplementedException("SPIR-V Instruction");
51} 51}
52 52
53void EmitSPIRV::EmitUnpackDouble2x32(EmitContext&) { 53void EmitUnpackDouble2x32(EmitContext&) {
54 throw NotImplementedException("SPIR-V Instruction"); 54 throw NotImplementedException("SPIR-V Instruction");
55} 55}
56 56
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp
index a7374c89d..348e4796d 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_composite.cpp
@@ -6,99 +6,99 @@
6 6
7namespace Shader::Backend::SPIRV { 7namespace Shader::Backend::SPIRV {
8 8
9void EmitSPIRV::EmitCompositeConstructU32x2(EmitContext&) { 9void EmitCompositeConstructU32x2(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction"); 10 throw NotImplementedException("SPIR-V Instruction");
11} 11}
12 12
13void EmitSPIRV::EmitCompositeConstructU32x3(EmitContext&) { 13void EmitCompositeConstructU32x3(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction"); 14 throw NotImplementedException("SPIR-V Instruction");
15} 15}
16 16
17void EmitSPIRV::EmitCompositeConstructU32x4(EmitContext&) { 17void EmitCompositeConstructU32x4(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction"); 18 throw NotImplementedException("SPIR-V Instruction");
19} 19}
20 20
21void EmitSPIRV::EmitCompositeExtractU32x2(EmitContext&) { 21void EmitCompositeExtractU32x2(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction"); 22 throw NotImplementedException("SPIR-V Instruction");
23} 23}
24 24
25Id EmitSPIRV::EmitCompositeExtractU32x3(EmitContext& ctx, Id vector, u32 index) { 25Id EmitCompositeExtractU32x3(EmitContext& ctx, Id vector, u32 index) {
26 return ctx.OpCompositeExtract(ctx.U32[1], vector, index); 26 return ctx.OpCompositeExtract(ctx.U32[1], vector, index);
27} 27}
28 28
29void EmitSPIRV::EmitCompositeExtractU32x4(EmitContext&) { 29void EmitCompositeExtractU32x4(EmitContext&) {
30 throw NotImplementedException("SPIR-V Instruction"); 30 throw NotImplementedException("SPIR-V Instruction");
31} 31}
32 32
33void EmitSPIRV::EmitCompositeConstructF16x2(EmitContext&) { 33void EmitCompositeConstructF16x2(EmitContext&) {
34 throw NotImplementedException("SPIR-V Instruction"); 34 throw NotImplementedException("SPIR-V Instruction");
35} 35}
36 36
37void EmitSPIRV::EmitCompositeConstructF16x3(EmitContext&) { 37void EmitCompositeConstructF16x3(EmitContext&) {
38 throw NotImplementedException("SPIR-V Instruction"); 38 throw NotImplementedException("SPIR-V Instruction");
39} 39}
40 40
41void EmitSPIRV::EmitCompositeConstructF16x4(EmitContext&) { 41void EmitCompositeConstructF16x4(EmitContext&) {
42 throw NotImplementedException("SPIR-V Instruction"); 42 throw NotImplementedException("SPIR-V Instruction");
43} 43}
44 44
45void EmitSPIRV::EmitCompositeExtractF16x2(EmitContext&) { 45void EmitCompositeExtractF16x2(EmitContext&) {
46 throw NotImplementedException("SPIR-V Instruction"); 46 throw NotImplementedException("SPIR-V Instruction");
47} 47}
48 48
49void EmitSPIRV::EmitCompositeExtractF16x3(EmitContext&) { 49void EmitCompositeExtractF16x3(EmitContext&) {
50 throw NotImplementedException("SPIR-V Instruction"); 50 throw NotImplementedException("SPIR-V Instruction");
51} 51}
52 52
53void EmitSPIRV::EmitCompositeExtractF16x4(EmitContext&) { 53void EmitCompositeExtractF16x4(EmitContext&) {
54 throw NotImplementedException("SPIR-V Instruction"); 54 throw NotImplementedException("SPIR-V Instruction");
55} 55}
56 56
57void EmitSPIRV::EmitCompositeConstructF32x2(EmitContext&) { 57void EmitCompositeConstructF32x2(EmitContext&) {
58 throw NotImplementedException("SPIR-V Instruction"); 58 throw NotImplementedException("SPIR-V Instruction");
59} 59}
60 60
61void EmitSPIRV::EmitCompositeConstructF32x3(EmitContext&) { 61void EmitCompositeConstructF32x3(EmitContext&) {
62 throw NotImplementedException("SPIR-V Instruction"); 62 throw NotImplementedException("SPIR-V Instruction");
63} 63}
64 64
65void EmitSPIRV::EmitCompositeConstructF32x4(EmitContext&) { 65void EmitCompositeConstructF32x4(EmitContext&) {
66 throw NotImplementedException("SPIR-V Instruction"); 66 throw NotImplementedException("SPIR-V Instruction");
67} 67}
68 68
69void EmitSPIRV::EmitCompositeExtractF32x2(EmitContext&) { 69void EmitCompositeExtractF32x2(EmitContext&) {
70 throw NotImplementedException("SPIR-V Instruction"); 70 throw NotImplementedException("SPIR-V Instruction");
71} 71}
72 72
73void EmitSPIRV::EmitCompositeExtractF32x3(EmitContext&) { 73void EmitCompositeExtractF32x3(EmitContext&) {
74 throw NotImplementedException("SPIR-V Instruction"); 74 throw NotImplementedException("SPIR-V Instruction");
75} 75}
76 76
77void EmitSPIRV::EmitCompositeExtractF32x4(EmitContext&) { 77void EmitCompositeExtractF32x4(EmitContext&) {
78 throw NotImplementedException("SPIR-V Instruction"); 78 throw NotImplementedException("SPIR-V Instruction");
79} 79}
80 80
81void EmitSPIRV::EmitCompositeConstructF64x2(EmitContext&) { 81void EmitCompositeConstructF64x2(EmitContext&) {
82 throw NotImplementedException("SPIR-V Instruction"); 82 throw NotImplementedException("SPIR-V Instruction");
83} 83}
84 84
85void EmitSPIRV::EmitCompositeConstructF64x3(EmitContext&) { 85void EmitCompositeConstructF64x3(EmitContext&) {
86 throw NotImplementedException("SPIR-V Instruction"); 86 throw NotImplementedException("SPIR-V Instruction");
87} 87}
88 88
89void EmitSPIRV::EmitCompositeConstructF64x4(EmitContext&) { 89void EmitCompositeConstructF64x4(EmitContext&) {
90 throw NotImplementedException("SPIR-V Instruction"); 90 throw NotImplementedException("SPIR-V Instruction");
91} 91}
92 92
93void EmitSPIRV::EmitCompositeExtractF64x2(EmitContext&) { 93void EmitCompositeExtractF64x2(EmitContext&) {
94 throw NotImplementedException("SPIR-V Instruction"); 94 throw NotImplementedException("SPIR-V Instruction");
95} 95}
96 96
97void EmitSPIRV::EmitCompositeExtractF64x3(EmitContext&) { 97void EmitCompositeExtractF64x3(EmitContext&) {
98 throw NotImplementedException("SPIR-V Instruction"); 98 throw NotImplementedException("SPIR-V Instruction");
99} 99}
100 100
101void EmitSPIRV::EmitCompositeExtractF64x4(EmitContext&) { 101void EmitCompositeExtractF64x4(EmitContext&) {
102 throw NotImplementedException("SPIR-V Instruction"); 102 throw NotImplementedException("SPIR-V Instruction");
103} 103}
104 104
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
index f4c9970eb..eb9c01c5a 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_context_get_set.cpp
@@ -6,31 +6,31 @@
6 6
7namespace Shader::Backend::SPIRV { 7namespace Shader::Backend::SPIRV {
8 8
9void EmitSPIRV::EmitGetRegister(EmitContext&) { 9void EmitGetRegister(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction"); 10 throw NotImplementedException("SPIR-V Instruction");
11} 11}
12 12
13void EmitSPIRV::EmitSetRegister(EmitContext&) { 13void EmitSetRegister(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction"); 14 throw NotImplementedException("SPIR-V Instruction");
15} 15}
16 16
17void EmitSPIRV::EmitGetPred(EmitContext&) { 17void EmitGetPred(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction"); 18 throw NotImplementedException("SPIR-V Instruction");
19} 19}
20 20
21void EmitSPIRV::EmitSetPred(EmitContext&) { 21void EmitSetPred(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction"); 22 throw NotImplementedException("SPIR-V Instruction");
23} 23}
24 24
25void EmitSPIRV::EmitSetGotoVariable(EmitContext&) { 25void EmitSetGotoVariable(EmitContext&) {
26 throw NotImplementedException("SPIR-V Instruction"); 26 throw NotImplementedException("SPIR-V Instruction");
27} 27}
28 28
29void EmitSPIRV::EmitGetGotoVariable(EmitContext&) { 29void EmitGetGotoVariable(EmitContext&) {
30 throw NotImplementedException("SPIR-V Instruction"); 30 throw NotImplementedException("SPIR-V Instruction");
31} 31}
32 32
33Id EmitSPIRV::EmitGetCbuf(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) { 33Id EmitGetCbuf(EmitContext& ctx, const IR::Value& binding, const IR::Value& offset) {
34 if (!binding.IsImmediate()) { 34 if (!binding.IsImmediate()) {
35 throw NotImplementedException("Constant buffer indexing"); 35 throw NotImplementedException("Constant buffer indexing");
36 } 36 }
@@ -43,59 +43,59 @@ Id EmitSPIRV::EmitGetCbuf(EmitContext& ctx, const IR::Value& binding, const IR::
43 return ctx.OpLoad(ctx.U32[1], access_chain); 43 return ctx.OpLoad(ctx.U32[1], access_chain);
44} 44}
45 45
46void EmitSPIRV::EmitGetAttribute(EmitContext&) { 46void EmitGetAttribute(EmitContext&) {
47 throw NotImplementedException("SPIR-V Instruction"); 47 throw NotImplementedException("SPIR-V Instruction");
48} 48}
49 49
50void EmitSPIRV::EmitSetAttribute(EmitContext&) { 50void EmitSetAttribute(EmitContext&) {
51 throw NotImplementedException("SPIR-V Instruction"); 51 throw NotImplementedException("SPIR-V Instruction");
52} 52}
53 53
54void EmitSPIRV::EmitGetAttributeIndexed(EmitContext&) { 54void EmitGetAttributeIndexed(EmitContext&) {
55 throw NotImplementedException("SPIR-V Instruction"); 55 throw NotImplementedException("SPIR-V Instruction");
56} 56}
57 57
58void EmitSPIRV::EmitSetAttributeIndexed(EmitContext&) { 58void EmitSetAttributeIndexed(EmitContext&) {
59 throw NotImplementedException("SPIR-V Instruction"); 59 throw NotImplementedException("SPIR-V Instruction");
60} 60}
61 61
62void EmitSPIRV::EmitGetZFlag(EmitContext&) { 62void EmitGetZFlag(EmitContext&) {
63 throw NotImplementedException("SPIR-V Instruction"); 63 throw NotImplementedException("SPIR-V Instruction");
64} 64}
65 65
66void EmitSPIRV::EmitGetSFlag(EmitContext&) { 66void EmitGetSFlag(EmitContext&) {
67 throw NotImplementedException("SPIR-V Instruction"); 67 throw NotImplementedException("SPIR-V Instruction");
68} 68}
69 69
70void EmitSPIRV::EmitGetCFlag(EmitContext&) { 70void EmitGetCFlag(EmitContext&) {
71 throw NotImplementedException("SPIR-V Instruction"); 71 throw NotImplementedException("SPIR-V Instruction");
72} 72}
73 73
74void EmitSPIRV::EmitGetOFlag(EmitContext&) { 74void EmitGetOFlag(EmitContext&) {
75 throw NotImplementedException("SPIR-V Instruction"); 75 throw NotImplementedException("SPIR-V Instruction");
76} 76}
77 77
78void EmitSPIRV::EmitSetZFlag(EmitContext&) { 78void EmitSetZFlag(EmitContext&) {
79 throw NotImplementedException("SPIR-V Instruction"); 79 throw NotImplementedException("SPIR-V Instruction");
80} 80}
81 81
82void EmitSPIRV::EmitSetSFlag(EmitContext&) { 82void EmitSetSFlag(EmitContext&) {
83 throw NotImplementedException("SPIR-V Instruction"); 83 throw NotImplementedException("SPIR-V Instruction");
84} 84}
85 85
86void EmitSPIRV::EmitSetCFlag(EmitContext&) { 86void EmitSetCFlag(EmitContext&) {
87 throw NotImplementedException("SPIR-V Instruction"); 87 throw NotImplementedException("SPIR-V Instruction");
88} 88}
89 89
90void EmitSPIRV::EmitSetOFlag(EmitContext&) { 90void EmitSetOFlag(EmitContext&) {
91 throw NotImplementedException("SPIR-V Instruction"); 91 throw NotImplementedException("SPIR-V Instruction");
92} 92}
93 93
94Id EmitSPIRV::EmitWorkgroupId(EmitContext& ctx) { 94Id EmitWorkgroupId(EmitContext& ctx) {
95 return ctx.OpLoad(ctx.U32[3], ctx.workgroup_id); 95 return ctx.OpLoad(ctx.U32[3], ctx.workgroup_id);
96} 96}
97 97
98Id EmitSPIRV::EmitLocalInvocationId(EmitContext& ctx) { 98Id EmitLocalInvocationId(EmitContext& ctx) {
99 return ctx.OpLoad(ctx.U32[3], ctx.local_invocation_id); 99 return ctx.OpLoad(ctx.U32[3], ctx.local_invocation_id);
100} 100}
101 101
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp
index 549c1907a..6c4199664 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_control_flow.cpp
@@ -6,25 +6,25 @@
6 6
7namespace Shader::Backend::SPIRV { 7namespace Shader::Backend::SPIRV {
8 8
9void EmitSPIRV::EmitBranch(EmitContext& ctx, IR::Block* label) { 9void EmitBranch(EmitContext& ctx, IR::Block* label) {
10 ctx.OpBranch(label->Definition<Id>()); 10 ctx.OpBranch(label->Definition<Id>());
11} 11}
12 12
13void EmitSPIRV::EmitBranchConditional(EmitContext& ctx, Id condition, IR::Block* true_label, 13void EmitBranchConditional(EmitContext& ctx, Id condition, IR::Block* true_label,
14 IR::Block* false_label) { 14 IR::Block* false_label) {
15 ctx.OpBranchConditional(condition, true_label->Definition<Id>(), false_label->Definition<Id>()); 15 ctx.OpBranchConditional(condition, true_label->Definition<Id>(), false_label->Definition<Id>());
16} 16}
17 17
18void EmitSPIRV::EmitLoopMerge(EmitContext& ctx, IR::Block* merge_label, IR::Block* continue_label) { 18void EmitLoopMerge(EmitContext& ctx, IR::Block* merge_label, IR::Block* continue_label) {
19 ctx.OpLoopMerge(merge_label->Definition<Id>(), continue_label->Definition<Id>(), 19 ctx.OpLoopMerge(merge_label->Definition<Id>(), continue_label->Definition<Id>(),
20 spv::LoopControlMask::MaskNone); 20 spv::LoopControlMask::MaskNone);
21} 21}
22 22
23void EmitSPIRV::EmitSelectionMerge(EmitContext& ctx, IR::Block* merge_label) { 23void EmitSelectionMerge(EmitContext& ctx, IR::Block* merge_label) {
24 ctx.OpSelectionMerge(merge_label->Definition<Id>(), spv::SelectionControlMask::MaskNone); 24 ctx.OpSelectionMerge(merge_label->Definition<Id>(), spv::SelectionControlMask::MaskNone);
25} 25}
26 26
27void EmitSPIRV::EmitReturn(EmitContext& ctx) { 27void EmitReturn(EmitContext& ctx) {
28 ctx.OpReturn(); 28 ctx.OpReturn();
29} 29}
30 30
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp
index c9bc121f8..d24fbb353 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_floating_point.cpp
@@ -33,187 +33,187 @@ Id Decorate(EmitContext& ctx, IR::Inst* inst, Id op) {
33 33
34} // Anonymous namespace 34} // Anonymous namespace
35 35
36void EmitSPIRV::EmitFPAbs16(EmitContext&) { 36void EmitFPAbs16(EmitContext&) {
37 throw NotImplementedException("SPIR-V Instruction"); 37 throw NotImplementedException("SPIR-V Instruction");
38} 38}
39 39
40void EmitSPIRV::EmitFPAbs32(EmitContext&) { 40void EmitFPAbs32(EmitContext&) {
41 throw NotImplementedException("SPIR-V Instruction"); 41 throw NotImplementedException("SPIR-V Instruction");
42} 42}
43 43
44void EmitSPIRV::EmitFPAbs64(EmitContext&) { 44void EmitFPAbs64(EmitContext&) {
45 throw NotImplementedException("SPIR-V Instruction"); 45 throw NotImplementedException("SPIR-V Instruction");
46} 46}
47 47
48Id EmitSPIRV::EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { 48Id EmitFPAdd16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
49 return Decorate(ctx, inst, ctx.OpFAdd(ctx.F16[1], a, b)); 49 return Decorate(ctx, inst, ctx.OpFAdd(ctx.F16[1], a, b));
50} 50}
51 51
52Id EmitSPIRV::EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { 52Id EmitFPAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
53 return Decorate(ctx, inst, ctx.OpFAdd(ctx.F32[1], a, b)); 53 return Decorate(ctx, inst, ctx.OpFAdd(ctx.F32[1], a, b));
54} 54}
55 55
56Id EmitSPIRV::EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { 56Id EmitFPAdd64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
57 return Decorate(ctx, inst, ctx.OpFAdd(ctx.F64[1], a, b)); 57 return Decorate(ctx, inst, ctx.OpFAdd(ctx.F64[1], a, b));
58} 58}
59 59
60Id EmitSPIRV::EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) { 60Id EmitFPFma16(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
61 return Decorate(ctx, inst, ctx.OpFma(ctx.F16[1], a, b, c)); 61 return Decorate(ctx, inst, ctx.OpFma(ctx.F16[1], a, b, c));
62} 62}
63 63
64Id EmitSPIRV::EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) { 64Id EmitFPFma32(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
65 return Decorate(ctx, inst, ctx.OpFma(ctx.F32[1], a, b, c)); 65 return Decorate(ctx, inst, ctx.OpFma(ctx.F32[1], a, b, c));
66} 66}
67 67
68Id EmitSPIRV::EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) { 68Id EmitFPFma64(EmitContext& ctx, IR::Inst* inst, Id a, Id b, Id c) {
69 return Decorate(ctx, inst, ctx.OpFma(ctx.F64[1], a, b, c)); 69 return Decorate(ctx, inst, ctx.OpFma(ctx.F64[1], a, b, c));
70} 70}
71 71
72void EmitSPIRV::EmitFPMax32(EmitContext&) { 72void EmitFPMax32(EmitContext&) {
73 throw NotImplementedException("SPIR-V Instruction"); 73 throw NotImplementedException("SPIR-V Instruction");
74} 74}
75 75
76void EmitSPIRV::EmitFPMax64(EmitContext&) { 76void EmitFPMax64(EmitContext&) {
77 throw NotImplementedException("SPIR-V Instruction"); 77 throw NotImplementedException("SPIR-V Instruction");
78} 78}
79 79
80void EmitSPIRV::EmitFPMin32(EmitContext&) { 80void EmitFPMin32(EmitContext&) {
81 throw NotImplementedException("SPIR-V Instruction"); 81 throw NotImplementedException("SPIR-V Instruction");
82} 82}
83 83
84void EmitSPIRV::EmitFPMin64(EmitContext&) { 84void EmitFPMin64(EmitContext&) {
85 throw NotImplementedException("SPIR-V Instruction"); 85 throw NotImplementedException("SPIR-V Instruction");
86} 86}
87 87
88Id EmitSPIRV::EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { 88Id EmitFPMul16(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
89 return Decorate(ctx, inst, ctx.OpFMul(ctx.F16[1], a, b)); 89 return Decorate(ctx, inst, ctx.OpFMul(ctx.F16[1], a, b));
90} 90}
91 91
92Id EmitSPIRV::EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { 92Id EmitFPMul32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
93 return Decorate(ctx, inst, ctx.OpFMul(ctx.F32[1], a, b)); 93 return Decorate(ctx, inst, ctx.OpFMul(ctx.F32[1], a, b));
94} 94}
95 95
96Id EmitSPIRV::EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { 96Id EmitFPMul64(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
97 return Decorate(ctx, inst, ctx.OpFMul(ctx.F64[1], a, b)); 97 return Decorate(ctx, inst, ctx.OpFMul(ctx.F64[1], a, b));
98} 98}
99 99
100void EmitSPIRV::EmitFPNeg16(EmitContext&) { 100void EmitFPNeg16(EmitContext&) {
101 throw NotImplementedException("SPIR-V Instruction"); 101 throw NotImplementedException("SPIR-V Instruction");
102} 102}
103 103
104void EmitSPIRV::EmitFPNeg32(EmitContext&) { 104void EmitFPNeg32(EmitContext&) {
105 throw NotImplementedException("SPIR-V Instruction"); 105 throw NotImplementedException("SPIR-V Instruction");
106} 106}
107 107
108void EmitSPIRV::EmitFPNeg64(EmitContext&) { 108void EmitFPNeg64(EmitContext&) {
109 throw NotImplementedException("SPIR-V Instruction"); 109 throw NotImplementedException("SPIR-V Instruction");
110} 110}
111 111
112void EmitSPIRV::EmitFPRecip32(EmitContext&) { 112void EmitFPRecip32(EmitContext&) {
113 throw NotImplementedException("SPIR-V Instruction"); 113 throw NotImplementedException("SPIR-V Instruction");
114} 114}
115 115
116void EmitSPIRV::EmitFPRecip64(EmitContext&) { 116void EmitFPRecip64(EmitContext&) {
117 throw NotImplementedException("SPIR-V Instruction"); 117 throw NotImplementedException("SPIR-V Instruction");
118} 118}
119 119
120void EmitSPIRV::EmitFPRecipSqrt32(EmitContext&) { 120void EmitFPRecipSqrt32(EmitContext&) {
121 throw NotImplementedException("SPIR-V Instruction"); 121 throw NotImplementedException("SPIR-V Instruction");
122} 122}
123 123
124void EmitSPIRV::EmitFPRecipSqrt64(EmitContext&) { 124void EmitFPRecipSqrt64(EmitContext&) {
125 throw NotImplementedException("SPIR-V Instruction"); 125 throw NotImplementedException("SPIR-V Instruction");
126} 126}
127 127
128void EmitSPIRV::EmitFPSqrt(EmitContext&) { 128void EmitFPSqrt(EmitContext&) {
129 throw NotImplementedException("SPIR-V Instruction"); 129 throw NotImplementedException("SPIR-V Instruction");
130} 130}
131 131
132void EmitSPIRV::EmitFPSin(EmitContext&) { 132void EmitFPSin(EmitContext&) {
133 throw NotImplementedException("SPIR-V Instruction"); 133 throw NotImplementedException("SPIR-V Instruction");
134} 134}
135 135
136void EmitSPIRV::EmitFPSinNotReduced(EmitContext&) { 136void EmitFPSinNotReduced(EmitContext&) {
137 throw NotImplementedException("SPIR-V Instruction"); 137 throw NotImplementedException("SPIR-V Instruction");
138} 138}
139 139
140void EmitSPIRV::EmitFPExp2(EmitContext&) { 140void EmitFPExp2(EmitContext&) {
141 throw NotImplementedException("SPIR-V Instruction"); 141 throw NotImplementedException("SPIR-V Instruction");
142} 142}
143 143
144void EmitSPIRV::EmitFPExp2NotReduced(EmitContext&) { 144void EmitFPExp2NotReduced(EmitContext&) {
145 throw NotImplementedException("SPIR-V Instruction"); 145 throw NotImplementedException("SPIR-V Instruction");
146} 146}
147 147
148void EmitSPIRV::EmitFPCos(EmitContext&) { 148void EmitFPCos(EmitContext&) {
149 throw NotImplementedException("SPIR-V Instruction"); 149 throw NotImplementedException("SPIR-V Instruction");
150} 150}
151 151
152void EmitSPIRV::EmitFPCosNotReduced(EmitContext&) { 152void EmitFPCosNotReduced(EmitContext&) {
153 throw NotImplementedException("SPIR-V Instruction"); 153 throw NotImplementedException("SPIR-V Instruction");
154} 154}
155 155
156void EmitSPIRV::EmitFPLog2(EmitContext&) { 156void EmitFPLog2(EmitContext&) {
157 throw NotImplementedException("SPIR-V Instruction"); 157 throw NotImplementedException("SPIR-V Instruction");
158} 158}
159 159
160void EmitSPIRV::EmitFPSaturate16(EmitContext&) { 160void EmitFPSaturate16(EmitContext&) {
161 throw NotImplementedException("SPIR-V Instruction"); 161 throw NotImplementedException("SPIR-V Instruction");
162} 162}
163 163
164void EmitSPIRV::EmitFPSaturate32(EmitContext&) { 164void EmitFPSaturate32(EmitContext&) {
165 throw NotImplementedException("SPIR-V Instruction"); 165 throw NotImplementedException("SPIR-V Instruction");
166} 166}
167 167
168void EmitSPIRV::EmitFPSaturate64(EmitContext&) { 168void EmitFPSaturate64(EmitContext&) {
169 throw NotImplementedException("SPIR-V Instruction"); 169 throw NotImplementedException("SPIR-V Instruction");
170} 170}
171 171
172void EmitSPIRV::EmitFPRoundEven16(EmitContext&) { 172void EmitFPRoundEven16(EmitContext&) {
173 throw NotImplementedException("SPIR-V Instruction"); 173 throw NotImplementedException("SPIR-V Instruction");
174} 174}
175 175
176void EmitSPIRV::EmitFPRoundEven32(EmitContext&) { 176void EmitFPRoundEven32(EmitContext&) {
177 throw NotImplementedException("SPIR-V Instruction"); 177 throw NotImplementedException("SPIR-V Instruction");
178} 178}
179 179
180void EmitSPIRV::EmitFPRoundEven64(EmitContext&) { 180void EmitFPRoundEven64(EmitContext&) {
181 throw NotImplementedException("SPIR-V Instruction"); 181 throw NotImplementedException("SPIR-V Instruction");
182} 182}
183 183
184void EmitSPIRV::EmitFPFloor16(EmitContext&) { 184void EmitFPFloor16(EmitContext&) {
185 throw NotImplementedException("SPIR-V Instruction"); 185 throw NotImplementedException("SPIR-V Instruction");
186} 186}
187 187
188void EmitSPIRV::EmitFPFloor32(EmitContext&) { 188void EmitFPFloor32(EmitContext&) {
189 throw NotImplementedException("SPIR-V Instruction"); 189 throw NotImplementedException("SPIR-V Instruction");
190} 190}
191 191
192void EmitSPIRV::EmitFPFloor64(EmitContext&) { 192void EmitFPFloor64(EmitContext&) {
193 throw NotImplementedException("SPIR-V Instruction"); 193 throw NotImplementedException("SPIR-V Instruction");
194} 194}
195 195
196void EmitSPIRV::EmitFPCeil16(EmitContext&) { 196void EmitFPCeil16(EmitContext&) {
197 throw NotImplementedException("SPIR-V Instruction"); 197 throw NotImplementedException("SPIR-V Instruction");
198} 198}
199 199
200void EmitSPIRV::EmitFPCeil32(EmitContext&) { 200void EmitFPCeil32(EmitContext&) {
201 throw NotImplementedException("SPIR-V Instruction"); 201 throw NotImplementedException("SPIR-V Instruction");
202} 202}
203 203
204void EmitSPIRV::EmitFPCeil64(EmitContext&) { 204void EmitFPCeil64(EmitContext&) {
205 throw NotImplementedException("SPIR-V Instruction"); 205 throw NotImplementedException("SPIR-V Instruction");
206} 206}
207 207
208void EmitSPIRV::EmitFPTrunc16(EmitContext&) { 208void EmitFPTrunc16(EmitContext&) {
209 throw NotImplementedException("SPIR-V Instruction"); 209 throw NotImplementedException("SPIR-V Instruction");
210} 210}
211 211
212void EmitSPIRV::EmitFPTrunc32(EmitContext&) { 212void EmitFPTrunc32(EmitContext&) {
213 throw NotImplementedException("SPIR-V Instruction"); 213 throw NotImplementedException("SPIR-V Instruction");
214} 214}
215 215
216void EmitSPIRV::EmitFPTrunc64(EmitContext&) { 216void EmitFPTrunc64(EmitContext&) {
217 throw NotImplementedException("SPIR-V Instruction"); 217 throw NotImplementedException("SPIR-V Instruction");
218} 218}
219 219
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 32af94a73..a1d16b81e 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -6,126 +6,126 @@
6 6
7namespace Shader::Backend::SPIRV { 7namespace Shader::Backend::SPIRV {
8 8
9Id EmitSPIRV::EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) { 9Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
10 if (inst->HasAssociatedPseudoOperation()) { 10 if (inst->HasAssociatedPseudoOperation()) {
11 throw NotImplementedException("Pseudo-operations on IAdd32"); 11 throw NotImplementedException("Pseudo-operations on IAdd32");
12 } 12 }
13 return ctx.OpIAdd(ctx.U32[1], a, b); 13 return ctx.OpIAdd(ctx.U32[1], a, b);
14} 14}
15 15
16void EmitSPIRV::EmitIAdd64(EmitContext&) { 16void EmitIAdd64(EmitContext&) {
17 throw NotImplementedException("SPIR-V Instruction"); 17 throw NotImplementedException("SPIR-V Instruction");
18} 18}
19 19
20Id EmitSPIRV::EmitISub32(EmitContext& ctx, Id a, Id b) { 20Id EmitISub32(EmitContext& ctx, Id a, Id b) {
21 return ctx.OpISub(ctx.U32[1], a, b); 21 return ctx.OpISub(ctx.U32[1], a, b);
22} 22}
23 23
24void EmitSPIRV::EmitISub64(EmitContext&) { 24void EmitISub64(EmitContext&) {
25 throw NotImplementedException("SPIR-V Instruction"); 25 throw NotImplementedException("SPIR-V Instruction");
26} 26}
27 27
28Id EmitSPIRV::EmitIMul32(EmitContext& ctx, Id a, Id b) { 28Id EmitIMul32(EmitContext& ctx, Id a, Id b) {
29 return ctx.OpIMul(ctx.U32[1], a, b); 29 return ctx.OpIMul(ctx.U32[1], a, b);
30} 30}
31 31
32void EmitSPIRV::EmitINeg32(EmitContext&) { 32void EmitINeg32(EmitContext&) {
33 throw NotImplementedException("SPIR-V Instruction"); 33 throw NotImplementedException("SPIR-V Instruction");
34} 34}
35 35
36void EmitSPIRV::EmitIAbs32(EmitContext&) { 36void EmitIAbs32(EmitContext&) {
37 throw NotImplementedException("SPIR-V Instruction"); 37 throw NotImplementedException("SPIR-V Instruction");
38} 38}
39 39
40Id EmitSPIRV::EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) { 40Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
41 return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift); 41 return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
42} 42}
43 43
44void EmitSPIRV::EmitShiftRightLogical32(EmitContext&) { 44void EmitShiftRightLogical32(EmitContext&) {
45 throw NotImplementedException("SPIR-V Instruction"); 45 throw NotImplementedException("SPIR-V Instruction");
46} 46}
47 47
48void EmitSPIRV::EmitShiftRightArithmetic32(EmitContext&) { 48void EmitShiftRightArithmetic32(EmitContext&) {
49 throw NotImplementedException("SPIR-V Instruction"); 49 throw NotImplementedException("SPIR-V Instruction");
50} 50}
51 51
52void EmitSPIRV::EmitBitwiseAnd32(EmitContext&) { 52void EmitBitwiseAnd32(EmitContext&) {
53 throw NotImplementedException("SPIR-V Instruction"); 53 throw NotImplementedException("SPIR-V Instruction");
54} 54}
55 55
56void EmitSPIRV::EmitBitwiseOr32(EmitContext&) { 56void EmitBitwiseOr32(EmitContext&) {
57 throw NotImplementedException("SPIR-V Instruction"); 57 throw NotImplementedException("SPIR-V Instruction");
58} 58}
59 59
60void EmitSPIRV::EmitBitwiseXor32(EmitContext&) { 60void EmitBitwiseXor32(EmitContext&) {
61 throw NotImplementedException("SPIR-V Instruction"); 61 throw NotImplementedException("SPIR-V Instruction");
62} 62}
63 63
64void EmitSPIRV::EmitBitFieldInsert(EmitContext&) { 64void EmitBitFieldInsert(EmitContext&) {
65 throw NotImplementedException("SPIR-V Instruction"); 65 throw NotImplementedException("SPIR-V Instruction");
66} 66}
67 67
68void EmitSPIRV::EmitBitFieldSExtract(EmitContext&) { 68void EmitBitFieldSExtract(EmitContext&) {
69 throw NotImplementedException("SPIR-V Instruction"); 69 throw NotImplementedException("SPIR-V Instruction");
70} 70}
71 71
72Id EmitSPIRV::EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) { 72Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
73 return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count); 73 return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
74} 74}
75 75
76Id EmitSPIRV::EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) { 76Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
77 return ctx.OpSLessThan(ctx.U1, lhs, rhs); 77 return ctx.OpSLessThan(ctx.U1, lhs, rhs);
78} 78}
79 79
80void EmitSPIRV::EmitULessThan(EmitContext&) { 80void EmitULessThan(EmitContext&) {
81 throw NotImplementedException("SPIR-V Instruction"); 81 throw NotImplementedException("SPIR-V Instruction");
82} 82}
83 83
84void EmitSPIRV::EmitIEqual(EmitContext&) { 84void EmitIEqual(EmitContext&) {
85 throw NotImplementedException("SPIR-V Instruction"); 85 throw NotImplementedException("SPIR-V Instruction");
86} 86}
87 87
88void EmitSPIRV::EmitSLessThanEqual(EmitContext&) { 88void EmitSLessThanEqual(EmitContext&) {
89 throw NotImplementedException("SPIR-V Instruction"); 89 throw NotImplementedException("SPIR-V Instruction");
90} 90}
91 91
92void EmitSPIRV::EmitULessThanEqual(EmitContext&) { 92void EmitULessThanEqual(EmitContext&) {
93 throw NotImplementedException("SPIR-V Instruction"); 93 throw NotImplementedException("SPIR-V Instruction");
94} 94}
95 95
96Id EmitSPIRV::EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) { 96Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
97 return ctx.OpSGreaterThan(ctx.U1, lhs, rhs); 97 return ctx.OpSGreaterThan(ctx.U1, lhs, rhs);
98} 98}
99 99
100void EmitSPIRV::EmitUGreaterThan(EmitContext&) { 100void EmitUGreaterThan(EmitContext&) {
101 throw NotImplementedException("SPIR-V Instruction"); 101 throw NotImplementedException("SPIR-V Instruction");
102} 102}
103 103
104void EmitSPIRV::EmitINotEqual(EmitContext&) { 104void EmitINotEqual(EmitContext&) {
105 throw NotImplementedException("SPIR-V Instruction"); 105 throw NotImplementedException("SPIR-V Instruction");
106} 106}
107 107
108void EmitSPIRV::EmitSGreaterThanEqual(EmitContext&) { 108void EmitSGreaterThanEqual(EmitContext&) {
109 throw NotImplementedException("SPIR-V Instruction"); 109 throw NotImplementedException("SPIR-V Instruction");
110} 110}
111 111
112Id EmitSPIRV::EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) { 112Id EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
113 return ctx.OpUGreaterThanEqual(ctx.U1, lhs, rhs); 113 return ctx.OpUGreaterThanEqual(ctx.U1, lhs, rhs);
114} 114}
115 115
116void EmitSPIRV::EmitLogicalOr(EmitContext&) { 116void EmitLogicalOr(EmitContext&) {
117 throw NotImplementedException("SPIR-V Instruction"); 117 throw NotImplementedException("SPIR-V Instruction");
118} 118}
119 119
120void EmitSPIRV::EmitLogicalAnd(EmitContext&) { 120void EmitLogicalAnd(EmitContext&) {
121 throw NotImplementedException("SPIR-V Instruction"); 121 throw NotImplementedException("SPIR-V Instruction");
122} 122}
123 123
124void EmitSPIRV::EmitLogicalXor(EmitContext&) { 124void EmitLogicalXor(EmitContext&) {
125 throw NotImplementedException("SPIR-V Instruction"); 125 throw NotImplementedException("SPIR-V Instruction");
126} 126}
127 127
128void EmitSPIRV::EmitLogicalNot(EmitContext&) { 128void EmitLogicalNot(EmitContext&) {
129 throw NotImplementedException("SPIR-V Instruction"); 129 throw NotImplementedException("SPIR-V Instruction");
130} 130}
131 131
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp
index 7b43c4ed8..ff2f4fb74 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_logical.cpp
@@ -6,83 +6,83 @@
6 6
7namespace Shader::Backend::SPIRV { 7namespace Shader::Backend::SPIRV {
8 8
9void EmitSPIRV::EmitConvertS16F16(EmitContext&) { 9void EmitConvertS16F16(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction"); 10 throw NotImplementedException("SPIR-V Instruction");
11} 11}
12 12
13void EmitSPIRV::EmitConvertS16F32(EmitContext&) { 13void EmitConvertS16F32(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction"); 14 throw NotImplementedException("SPIR-V Instruction");
15} 15}
16 16
17void EmitSPIRV::EmitConvertS16F64(EmitContext&) { 17void EmitConvertS16F64(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction"); 18 throw NotImplementedException("SPIR-V Instruction");
19} 19}
20 20
21void EmitSPIRV::EmitConvertS32F16(EmitContext&) { 21void EmitConvertS32F16(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction"); 22 throw NotImplementedException("SPIR-V Instruction");
23} 23}
24 24
25void EmitSPIRV::EmitConvertS32F32(EmitContext&) { 25void EmitConvertS32F32(EmitContext&) {
26 throw NotImplementedException("SPIR-V Instruction"); 26 throw NotImplementedException("SPIR-V Instruction");
27} 27}
28 28
29void EmitSPIRV::EmitConvertS32F64(EmitContext&) { 29void EmitConvertS32F64(EmitContext&) {
30 throw NotImplementedException("SPIR-V Instruction"); 30 throw NotImplementedException("SPIR-V Instruction");
31} 31}
32 32
33void EmitSPIRV::EmitConvertS64F16(EmitContext&) { 33void EmitConvertS64F16(EmitContext&) {
34 throw NotImplementedException("SPIR-V Instruction"); 34 throw NotImplementedException("SPIR-V Instruction");
35} 35}
36 36
37void EmitSPIRV::EmitConvertS64F32(EmitContext&) { 37void EmitConvertS64F32(EmitContext&) {
38 throw NotImplementedException("SPIR-V Instruction"); 38 throw NotImplementedException("SPIR-V Instruction");
39} 39}
40 40
41void EmitSPIRV::EmitConvertS64F64(EmitContext&) { 41void EmitConvertS64F64(EmitContext&) {
42 throw NotImplementedException("SPIR-V Instruction"); 42 throw NotImplementedException("SPIR-V Instruction");
43} 43}
44 44
45void EmitSPIRV::EmitConvertU16F16(EmitContext&) { 45void EmitConvertU16F16(EmitContext&) {
46 throw NotImplementedException("SPIR-V Instruction"); 46 throw NotImplementedException("SPIR-V Instruction");
47} 47}
48 48
49void EmitSPIRV::EmitConvertU16F32(EmitContext&) { 49void EmitConvertU16F32(EmitContext&) {
50 throw NotImplementedException("SPIR-V Instruction"); 50 throw NotImplementedException("SPIR-V Instruction");
51} 51}
52 52
53void EmitSPIRV::EmitConvertU16F64(EmitContext&) { 53void EmitConvertU16F64(EmitContext&) {
54 throw NotImplementedException("SPIR-V Instruction"); 54 throw NotImplementedException("SPIR-V Instruction");
55} 55}
56 56
57void EmitSPIRV::EmitConvertU32F16(EmitContext&) { 57void EmitConvertU32F16(EmitContext&) {
58 throw NotImplementedException("SPIR-V Instruction"); 58 throw NotImplementedException("SPIR-V Instruction");
59} 59}
60 60
61void EmitSPIRV::EmitConvertU32F32(EmitContext&) { 61void EmitConvertU32F32(EmitContext&) {
62 throw NotImplementedException("SPIR-V Instruction"); 62 throw NotImplementedException("SPIR-V Instruction");
63} 63}
64 64
65void EmitSPIRV::EmitConvertU32F64(EmitContext&) { 65void EmitConvertU32F64(EmitContext&) {
66 throw NotImplementedException("SPIR-V Instruction"); 66 throw NotImplementedException("SPIR-V Instruction");
67} 67}
68 68
69void EmitSPIRV::EmitConvertU64F16(EmitContext&) { 69void EmitConvertU64F16(EmitContext&) {
70 throw NotImplementedException("SPIR-V Instruction"); 70 throw NotImplementedException("SPIR-V Instruction");
71} 71}
72 72
73void EmitSPIRV::EmitConvertU64F32(EmitContext&) { 73void EmitConvertU64F32(EmitContext&) {
74 throw NotImplementedException("SPIR-V Instruction"); 74 throw NotImplementedException("SPIR-V Instruction");
75} 75}
76 76
77void EmitSPIRV::EmitConvertU64F64(EmitContext&) { 77void EmitConvertU64F64(EmitContext&) {
78 throw NotImplementedException("SPIR-V Instruction"); 78 throw NotImplementedException("SPIR-V Instruction");
79} 79}
80 80
81void EmitSPIRV::EmitConvertU64U32(EmitContext&) { 81void EmitConvertU64U32(EmitContext&) {
82 throw NotImplementedException("SPIR-V Instruction"); 82 throw NotImplementedException("SPIR-V Instruction");
83} 83}
84 84
85void EmitSPIRV::EmitConvertU32U64(EmitContext&) { 85void EmitConvertU32U64(EmitContext&) {
86 throw NotImplementedException("SPIR-V Instruction"); 86 throw NotImplementedException("SPIR-V Instruction");
87} 87}
88 88
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_memory.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_memory.cpp
index 5769a3c95..77d698ffd 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_memory.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_memory.cpp
@@ -22,79 +22,79 @@ static Id StorageIndex(EmitContext& ctx, const IR::Value& offset, size_t element
22 return ctx.OpShiftRightLogical(ctx.U32[1], index, shift_id); 22 return ctx.OpShiftRightLogical(ctx.U32[1], index, shift_id);
23} 23}
24 24
25void EmitSPIRV::EmitLoadGlobalU8(EmitContext&) { 25void EmitLoadGlobalU8(EmitContext&) {
26 throw NotImplementedException("SPIR-V Instruction"); 26 throw NotImplementedException("SPIR-V Instruction");
27} 27}
28 28
29void EmitSPIRV::EmitLoadGlobalS8(EmitContext&) { 29void EmitLoadGlobalS8(EmitContext&) {
30 throw NotImplementedException("SPIR-V Instruction"); 30 throw NotImplementedException("SPIR-V Instruction");
31} 31}
32 32
33void EmitSPIRV::EmitLoadGlobalU16(EmitContext&) { 33void EmitLoadGlobalU16(EmitContext&) {
34 throw NotImplementedException("SPIR-V Instruction"); 34 throw NotImplementedException("SPIR-V Instruction");
35} 35}
36 36
37void EmitSPIRV::EmitLoadGlobalS16(EmitContext&) { 37void EmitLoadGlobalS16(EmitContext&) {
38 throw NotImplementedException("SPIR-V Instruction"); 38 throw NotImplementedException("SPIR-V Instruction");
39} 39}
40 40
41void EmitSPIRV::EmitLoadGlobal32(EmitContext&) { 41void EmitLoadGlobal32(EmitContext&) {
42 throw NotImplementedException("SPIR-V Instruction"); 42 throw NotImplementedException("SPIR-V Instruction");
43} 43}
44 44
45void EmitSPIRV::EmitLoadGlobal64(EmitContext&) { 45void EmitLoadGlobal64(EmitContext&) {
46 throw NotImplementedException("SPIR-V Instruction"); 46 throw NotImplementedException("SPIR-V Instruction");
47} 47}
48 48
49void EmitSPIRV::EmitLoadGlobal128(EmitContext&) { 49void EmitLoadGlobal128(EmitContext&) {
50 throw NotImplementedException("SPIR-V Instruction"); 50 throw NotImplementedException("SPIR-V Instruction");
51} 51}
52 52
53void EmitSPIRV::EmitWriteGlobalU8(EmitContext&) { 53void EmitWriteGlobalU8(EmitContext&) {
54 throw NotImplementedException("SPIR-V Instruction"); 54 throw NotImplementedException("SPIR-V Instruction");
55} 55}
56 56
57void EmitSPIRV::EmitWriteGlobalS8(EmitContext&) { 57void EmitWriteGlobalS8(EmitContext&) {
58 throw NotImplementedException("SPIR-V Instruction"); 58 throw NotImplementedException("SPIR-V Instruction");
59} 59}
60 60
61void EmitSPIRV::EmitWriteGlobalU16(EmitContext&) { 61void EmitWriteGlobalU16(EmitContext&) {
62 throw NotImplementedException("SPIR-V Instruction"); 62 throw NotImplementedException("SPIR-V Instruction");
63} 63}
64 64
65void EmitSPIRV::EmitWriteGlobalS16(EmitContext&) { 65void EmitWriteGlobalS16(EmitContext&) {
66 throw NotImplementedException("SPIR-V Instruction"); 66 throw NotImplementedException("SPIR-V Instruction");
67} 67}
68 68
69void EmitSPIRV::EmitWriteGlobal32(EmitContext&) { 69void EmitWriteGlobal32(EmitContext&) {
70 throw NotImplementedException("SPIR-V Instruction"); 70 throw NotImplementedException("SPIR-V Instruction");
71} 71}
72 72
73void EmitSPIRV::EmitWriteGlobal64(EmitContext&) { 73void EmitWriteGlobal64(EmitContext&) {
74 throw NotImplementedException("SPIR-V Instruction"); 74 throw NotImplementedException("SPIR-V Instruction");
75} 75}
76 76
77void EmitSPIRV::EmitWriteGlobal128(EmitContext&) { 77void EmitWriteGlobal128(EmitContext&) {
78 throw NotImplementedException("SPIR-V Instruction"); 78 throw NotImplementedException("SPIR-V Instruction");
79} 79}
80 80
81void EmitSPIRV::EmitLoadStorageU8(EmitContext&) { 81void EmitLoadStorageU8(EmitContext&) {
82 throw NotImplementedException("SPIR-V Instruction"); 82 throw NotImplementedException("SPIR-V Instruction");
83} 83}
84 84
85void EmitSPIRV::EmitLoadStorageS8(EmitContext&) { 85void EmitLoadStorageS8(EmitContext&) {
86 throw NotImplementedException("SPIR-V Instruction"); 86 throw NotImplementedException("SPIR-V Instruction");
87} 87}
88 88
89void EmitSPIRV::EmitLoadStorageU16(EmitContext&) { 89void EmitLoadStorageU16(EmitContext&) {
90 throw NotImplementedException("SPIR-V Instruction"); 90 throw NotImplementedException("SPIR-V Instruction");
91} 91}
92 92
93void EmitSPIRV::EmitLoadStorageS16(EmitContext&) { 93void EmitLoadStorageS16(EmitContext&) {
94 throw NotImplementedException("SPIR-V Instruction"); 94 throw NotImplementedException("SPIR-V Instruction");
95} 95}
96 96
97Id EmitSPIRV::EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding, 97Id EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding,
98 const IR::Value& offset) { 98 const IR::Value& offset) {
99 if (!binding.IsImmediate()) { 99 if (!binding.IsImmediate()) {
100 throw NotImplementedException("Dynamic storage buffer indexing"); 100 throw NotImplementedException("Dynamic storage buffer indexing");
@@ -105,31 +105,31 @@ Id EmitSPIRV::EmitLoadStorage32(EmitContext& ctx, const IR::Value& binding,
105 return ctx.OpLoad(ctx.U32[1], pointer); 105 return ctx.OpLoad(ctx.U32[1], pointer);
106} 106}
107 107
108void EmitSPIRV::EmitLoadStorage64(EmitContext&) { 108void EmitLoadStorage64(EmitContext&) {
109 throw NotImplementedException("SPIR-V Instruction"); 109 throw NotImplementedException("SPIR-V Instruction");
110} 110}
111 111
112void EmitSPIRV::EmitLoadStorage128(EmitContext&) { 112void EmitLoadStorage128(EmitContext&) {
113 throw NotImplementedException("SPIR-V Instruction"); 113 throw NotImplementedException("SPIR-V Instruction");
114} 114}
115 115
116void EmitSPIRV::EmitWriteStorageU8(EmitContext&) { 116void EmitWriteStorageU8(EmitContext&) {
117 throw NotImplementedException("SPIR-V Instruction"); 117 throw NotImplementedException("SPIR-V Instruction");
118} 118}
119 119
120void EmitSPIRV::EmitWriteStorageS8(EmitContext&) { 120void EmitWriteStorageS8(EmitContext&) {
121 throw NotImplementedException("SPIR-V Instruction"); 121 throw NotImplementedException("SPIR-V Instruction");
122} 122}
123 123
124void EmitSPIRV::EmitWriteStorageU16(EmitContext&) { 124void EmitWriteStorageU16(EmitContext&) {
125 throw NotImplementedException("SPIR-V Instruction"); 125 throw NotImplementedException("SPIR-V Instruction");
126} 126}
127 127
128void EmitSPIRV::EmitWriteStorageS16(EmitContext&) { 128void EmitWriteStorageS16(EmitContext&) {
129 throw NotImplementedException("SPIR-V Instruction"); 129 throw NotImplementedException("SPIR-V Instruction");
130} 130}
131 131
132void EmitSPIRV::EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding, 132void EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding,
133 const IR::Value& offset, Id value) { 133 const IR::Value& offset, Id value) {
134 if (!binding.IsImmediate()) { 134 if (!binding.IsImmediate()) {
135 throw NotImplementedException("Dynamic storage buffer indexing"); 135 throw NotImplementedException("Dynamic storage buffer indexing");
@@ -140,11 +140,11 @@ void EmitSPIRV::EmitWriteStorage32(EmitContext& ctx, const IR::Value& binding,
140 ctx.OpStore(pointer, value); 140 ctx.OpStore(pointer, value);
141} 141}
142 142
143void EmitSPIRV::EmitWriteStorage64(EmitContext&) { 143void EmitWriteStorage64(EmitContext&) {
144 throw NotImplementedException("SPIR-V Instruction"); 144 throw NotImplementedException("SPIR-V Instruction");
145} 145}
146 146
147void EmitSPIRV::EmitWriteStorage128(EmitContext&) { 147void EmitWriteStorage128(EmitContext&) {
148 throw NotImplementedException("SPIR-V Instruction"); 148 throw NotImplementedException("SPIR-V Instruction");
149} 149}
150 150
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
index 40a856f72..8d5062724 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_select.cpp
@@ -6,19 +6,19 @@
6 6
7namespace Shader::Backend::SPIRV { 7namespace Shader::Backend::SPIRV {
8 8
9void EmitSPIRV::EmitSelect8(EmitContext&) { 9void EmitSelect8(EmitContext&) {
10 throw NotImplementedException("SPIR-V Instruction"); 10 throw NotImplementedException("SPIR-V Instruction");
11} 11}
12 12
13void EmitSPIRV::EmitSelect16(EmitContext&) { 13void EmitSelect16(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction"); 14 throw NotImplementedException("SPIR-V Instruction");
15} 15}
16 16
17void EmitSPIRV::EmitSelect32(EmitContext&) { 17void EmitSelect32(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction"); 18 throw NotImplementedException("SPIR-V Instruction");
19} 19}
20 20
21void EmitSPIRV::EmitSelect64(EmitContext&) { 21void EmitSelect64(EmitContext&) {
22 throw NotImplementedException("SPIR-V Instruction"); 22 throw NotImplementedException("SPIR-V Instruction");
23} 23}
24 24
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp
index c1ed8f281..19b06dbe4 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp
@@ -6,23 +6,23 @@
6 6
7namespace Shader::Backend::SPIRV { 7namespace Shader::Backend::SPIRV {
8 8
9Id EmitSPIRV::EmitUndefU1(EmitContext& ctx) { 9Id EmitUndefU1(EmitContext& ctx) {
10 return ctx.OpUndef(ctx.U1); 10 return ctx.OpUndef(ctx.U1);
11} 11}
12 12
13Id EmitSPIRV::EmitUndefU8(EmitContext&) { 13Id EmitUndefU8(EmitContext&) {
14 throw NotImplementedException("SPIR-V Instruction"); 14 throw NotImplementedException("SPIR-V Instruction");
15} 15}
16 16
17Id EmitSPIRV::EmitUndefU16(EmitContext&) { 17Id EmitUndefU16(EmitContext&) {
18 throw NotImplementedException("SPIR-V Instruction"); 18 throw NotImplementedException("SPIR-V Instruction");
19} 19}
20 20
21Id EmitSPIRV::EmitUndefU32(EmitContext& ctx) { 21Id EmitUndefU32(EmitContext& ctx) {
22 return ctx.OpUndef(ctx.U32[1]); 22 return ctx.OpUndef(ctx.U32[1]);
23} 23}
24 24
25Id EmitSPIRV::EmitUndefU64(EmitContext&) { 25Id EmitUndefU64(EmitContext&) {
26 throw NotImplementedException("SPIR-V Instruction"); 26 throw NotImplementedException("SPIR-V Instruction");
27} 27}
28 28
diff --git a/src/shader_recompiler/environment.h b/src/shader_recompiler/environment.h
index f6230e817..0ba681fb9 100644
--- a/src/shader_recompiler/environment.h
+++ b/src/shader_recompiler/environment.h
@@ -1,5 +1,7 @@
1#pragma once 1#pragma once
2 2
3#include <array>
4
3#include "common/common_types.h" 5#include "common/common_types.h"
4 6
5namespace Shader { 7namespace Shader {
@@ -8,7 +10,9 @@ class Environment {
8public: 10public:
9 virtual ~Environment() = default; 11 virtual ~Environment() = default;
10 12
11 [[nodiscard]] virtual u64 ReadInstruction(u32 address) const = 0; 13 [[nodiscard]] virtual u64 ReadInstruction(u32 address) = 0;
14
15 [[nodiscard]] virtual std::array<u32, 3> WorkgroupSize() = 0;
12}; 16};
13 17
14} // namespace Shader 18} // namespace Shader
diff --git a/src/shader_recompiler/file_environment.cpp b/src/shader_recompiler/file_environment.cpp
index b34bf462b..5127523f9 100644
--- a/src/shader_recompiler/file_environment.cpp
+++ b/src/shader_recompiler/file_environment.cpp
@@ -29,7 +29,7 @@ FileEnvironment::FileEnvironment(const char* path) {
29 29
30FileEnvironment::~FileEnvironment() = default; 30FileEnvironment::~FileEnvironment() = default;
31 31
32u64 FileEnvironment::ReadInstruction(u32 offset) const { 32u64 FileEnvironment::ReadInstruction(u32 offset) {
33 if (offset % 8 != 0) { 33 if (offset % 8 != 0) {
34 throw InvalidArgument("offset={} is not aligned to 8", offset); 34 throw InvalidArgument("offset={} is not aligned to 8", offset);
35 } 35 }
@@ -39,4 +39,8 @@ u64 FileEnvironment::ReadInstruction(u32 offset) const {
39 return data[offset / 8]; 39 return data[offset / 8];
40} 40}
41 41
42std::array<u32, 3> FileEnvironment::WorkgroupSize() {
43 return {1, 1, 1};
44}
45
42} // namespace Shader 46} // namespace Shader
diff --git a/src/shader_recompiler/file_environment.h b/src/shader_recompiler/file_environment.h
index c294bc6fa..b8c4bbadd 100644
--- a/src/shader_recompiler/file_environment.h
+++ b/src/shader_recompiler/file_environment.h
@@ -12,7 +12,9 @@ public:
12 explicit FileEnvironment(const char* path); 12 explicit FileEnvironment(const char* path);
13 ~FileEnvironment() override; 13 ~FileEnvironment() override;
14 14
15 u64 ReadInstruction(u32 offset) const override; 15 u64 ReadInstruction(u32 offset) override;
16
17 std::array<u32, 3> WorkgroupSize() override;
16 18
17private: 19private:
18 std::vector<u64> data; 20 std::vector<u64> data;
diff --git a/src/shader_recompiler/frontend/ir/basic_block.cpp b/src/shader_recompiler/frontend/ir/basic_block.cpp
index 5ae91dd7d..ec029dfd6 100644
--- a/src/shader_recompiler/frontend/ir/basic_block.cpp
+++ b/src/shader_recompiler/frontend/ir/basic_block.cpp
@@ -127,6 +127,8 @@ static std::string ArgToIndex(const std::map<const Block*, size_t>& block_to_ind
127 return fmt::format("#{}", arg.U32()); 127 return fmt::format("#{}", arg.U32());
128 case Type::U64: 128 case Type::U64:
129 return fmt::format("#{}", arg.U64()); 129 return fmt::format("#{}", arg.U64());
130 case Type::F32:
131 return fmt::format("#{}", arg.F32());
130 case Type::Reg: 132 case Type::Reg:
131 return fmt::format("{}", arg.Reg()); 133 return fmt::format("{}", arg.Reg());
132 case Type::Pred: 134 case Type::Pred:
diff --git a/src/shader_recompiler/frontend/ir/post_order.cpp b/src/shader_recompiler/frontend/ir/post_order.cpp
index a48b8dec5..8709a2ea1 100644
--- a/src/shader_recompiler/frontend/ir/post_order.cpp
+++ b/src/shader_recompiler/frontend/ir/post_order.cpp
@@ -28,7 +28,7 @@ BlockList PostOrder(const BlockList& blocks) {
28 if (!visited.insert(branch).second) { 28 if (!visited.insert(branch).second) {
29 return false; 29 return false;
30 } 30 }
31 // Calling push_back twice is faster than insert on msvc 31 // Calling push_back twice is faster than insert on MSVC
32 block_stack.push_back(block); 32 block_stack.push_back(block);
33 block_stack.push_back(branch); 33 block_stack.push_back(branch);
34 return true; 34 return true;
diff --git a/src/shader_recompiler/frontend/maxwell/program.cpp b/src/shader_recompiler/frontend/maxwell/program.cpp
index 8331d576c..8c44ebb29 100644
--- a/src/shader_recompiler/frontend/maxwell/program.cpp
+++ b/src/shader_recompiler/frontend/maxwell/program.cpp
@@ -69,7 +69,7 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
69 Optimization::VerificationPass(function); 69 Optimization::VerificationPass(function);
70 } 70 }
71 Optimization::CollectShaderInfoPass(program); 71 Optimization::CollectShaderInfoPass(program);
72 //*/ 72 fmt::print(stdout, "{}\n", IR::DumpProgram(program));
73 return program; 73 return program;
74} 74}
75 75
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
index 3c9eaddd9..079e3497f 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
@@ -24,6 +24,14 @@ void TranslatorVisitor::F(IR::Reg dest_reg, const IR::F32& value) {
24 X(dest_reg, ir.BitCast<IR::U32>(value)); 24 X(dest_reg, ir.BitCast<IR::U32>(value));
25} 25}
26 26
27IR::U32 TranslatorVisitor::GetReg8(u64 insn) {
28 union {
29 u64 raw;
30 BitField<8, 8, IR::Reg> index;
31 } const reg{insn};
32 return X(reg.index);
33}
34
27IR::U32 TranslatorVisitor::GetReg20(u64 insn) { 35IR::U32 TranslatorVisitor::GetReg20(u64 insn) {
28 union { 36 union {
29 u64 raw; 37 u64 raw;
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.h b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.h
index b701605d7..8bd468244 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.h
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.h
@@ -301,6 +301,7 @@ public:
301 void X(IR::Reg dest_reg, const IR::U32& value); 301 void X(IR::Reg dest_reg, const IR::U32& value);
302 void F(IR::Reg dest_reg, const IR::F32& value); 302 void F(IR::Reg dest_reg, const IR::F32& value);
303 303
304 [[nodiscard]] IR::U32 GetReg8(u64 insn);
304 [[nodiscard]] IR::U32 GetReg20(u64 insn); 305 [[nodiscard]] IR::U32 GetReg20(u64 insn);
305 [[nodiscard]] IR::U32 GetReg39(u64 insn); 306 [[nodiscard]] IR::U32 GetReg39(u64 insn);
306 [[nodiscard]] IR::F32 GetReg20F(u64 insn); 307 [[nodiscard]] IR::F32 GetReg20F(u64 insn);
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
index 1f83d1068..c3c4b9abd 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
@@ -10,36 +10,35 @@
10 10
11namespace Shader::Maxwell { 11namespace Shader::Maxwell {
12namespace { 12namespace {
13union MOV { 13void MOV(TranslatorVisitor& v, u64 insn, const IR::U32& src, bool is_mov32i = false) {
14 u64 raw; 14 union {
15 BitField<0, 8, IR::Reg> dest_reg; 15 u64 raw;
16 BitField<20, 8, IR::Reg> src_reg; 16 BitField<0, 8, IR::Reg> dest_reg;
17 BitField<39, 4, u64> mask; 17 BitField<39, 4, u64> mask;
18}; 18 BitField<12, 4, u64> mov32i_mask;
19 19 } const mov{insn};
20void CheckMask(MOV mov) { 20
21 if (mov.mask != 0xf) { 21 if ((is_mov32i ? mov.mov32i_mask : mov.mask) != 0xf) {
22 throw NotImplementedException("Non-full move mask"); 22 throw NotImplementedException("Non-full move mask");
23 } 23 }
24 v.X(mov.dest_reg, src);
24} 25}
25} // Anonymous namespace 26} // Anonymous namespace
26 27
27void TranslatorVisitor::MOV_reg(u64 insn) { 28void TranslatorVisitor::MOV_reg(u64 insn) {
28 const MOV mov{insn}; 29 MOV(*this, insn, GetReg8(insn));
29 CheckMask(mov);
30 X(mov.dest_reg, X(mov.src_reg));
31} 30}
32 31
33void TranslatorVisitor::MOV_cbuf(u64 insn) { 32void TranslatorVisitor::MOV_cbuf(u64 insn) {
34 const MOV mov{insn}; 33 MOV(*this, insn, GetCbuf(insn));
35 CheckMask(mov);
36 X(mov.dest_reg, GetCbuf(insn));
37} 34}
38 35
39void TranslatorVisitor::MOV_imm(u64 insn) { 36void TranslatorVisitor::MOV_imm(u64 insn) {
40 const MOV mov{insn}; 37 MOV(*this, insn, GetImm20(insn));
41 CheckMask(mov); 38}
42 X(mov.dest_reg, GetImm20(insn)); 39
40void TranslatorVisitor::MOV32I(u64 insn) {
41 MOV(*this, insn, GetImm32(insn), true);
43} 42}
44 43
45} // namespace Shader::Maxwell 44} // namespace Shader::Maxwell
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
index 1bb160acb..6b2a1356b 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
@@ -617,10 +617,6 @@ void TranslatorVisitor::MEMBAR(u64) {
617 ThrowNotImplemented(Opcode::MEMBAR); 617 ThrowNotImplemented(Opcode::MEMBAR);
618} 618}
619 619
620void TranslatorVisitor::MOV32I(u64) {
621 ThrowNotImplemented(Opcode::MOV32I);
622}
623
624void TranslatorVisitor::NOP(u64) { 620void TranslatorVisitor::NOP(u64) {
625 ThrowNotImplemented(Opcode::NOP); 621 ThrowNotImplemented(Opcode::NOP);
626} 622}
diff --git a/src/shader_recompiler/main.cpp b/src/shader_recompiler/main.cpp
index 1610bb34e..050a37f18 100644
--- a/src/shader_recompiler/main.cpp
+++ b/src/shader_recompiler/main.cpp
@@ -76,5 +76,5 @@ int main() {
76 fmt::print(stdout, "{}\n", cfg.Dot()); 76 fmt::print(stdout, "{}\n", cfg.Dot());
77 IR::Program program{TranslateProgram(inst_pool, block_pool, env, cfg)}; 77 IR::Program program{TranslateProgram(inst_pool, block_pool, env, cfg)};
78 fmt::print(stdout, "{}\n", IR::DumpProgram(program)); 78 fmt::print(stdout, "{}\n", IR::DumpProgram(program));
79 Backend::SPIRV::EmitSPIRV spirv{program}; 79 void(Backend::SPIRV::EmitSPIRV(env, program));
80} 80}
diff --git a/src/shader_recompiler/profile.h b/src/shader_recompiler/profile.h
new file mode 100644
index 000000000..c96d783b7
--- /dev/null
+++ b/src/shader_recompiler/profile.h
@@ -0,0 +1,13 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#pragma once
6
7namespace Shader {
8
9struct Profile {
10 bool unified_descriptor_binding;
11};
12
13} // namespace Shader
diff --git a/src/shader_recompiler/recompiler.cpp b/src/shader_recompiler/recompiler.cpp
new file mode 100644
index 000000000..b25081e39
--- /dev/null
+++ b/src/shader_recompiler/recompiler.cpp
@@ -0,0 +1,27 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include <vector>
6
7#include "common/common_types.h"
8#include "shader_recompiler/backend/spirv/emit_spirv.h"
9#include "shader_recompiler/environment.h"
10#include "shader_recompiler/frontend/maxwell/control_flow.h"
11#include "shader_recompiler/frontend/maxwell/program.h"
12#include "shader_recompiler/object_pool.h"
13#include "shader_recompiler/recompiler.h"
14
15namespace Shader {
16
17std::pair<Info, std::vector<u32>> RecompileSPIRV(Environment& env, u32 start_address) {
18 ObjectPool<Maxwell::Flow::Block> flow_block_pool;
19 ObjectPool<IR::Inst> inst_pool;
20 ObjectPool<IR::Block> block_pool;
21
22 Maxwell::Flow::CFG cfg{env, flow_block_pool, start_address};
23 IR::Program program{Maxwell::TranslateProgram(inst_pool, block_pool, env, cfg)};
24 return {std::move(program.info), Backend::SPIRV::EmitSPIRV(env, program)};
25}
26
27} // namespace Shader
diff --git a/src/shader_recompiler/recompiler.h b/src/shader_recompiler/recompiler.h
new file mode 100644
index 000000000..4cb973878
--- /dev/null
+++ b/src/shader_recompiler/recompiler.h
@@ -0,0 +1,18 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#pragma once
6
7#include <utility>
8#include <vector>
9
10#include "common/common_types.h"
11#include "shader_recompiler/environment.h"
12#include "shader_recompiler/shader_info.h"
13
14namespace Shader {
15
16[[nodiscard]] std::pair<Info, std::vector<u32>> RecompileSPIRV(Environment& env, u32 start_address);
17
18} // namespace Shader
HIC SVNT DRACONES