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authorGravatar Fernando Sahmkow2023-08-18 18:30:31 +0200
committerGravatar Liam2023-08-18 22:17:02 -0400
commitc03f0b3c893f2bc2ae4f1e1825c5ac1453c36710 (patch)
tree3f7f14fad6574878a7c0f94fbe16d574b61cb95a /src/shader_recompiler/frontend
parentMerge pull request #11278 from Kelebek1/dma_sync (diff)
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Shader Recomnpiler: implement textuzreGrad 3D emulation constant propagation
Diffstat (limited to 'src/shader_recompiler/frontend')
-rw-r--r--src/shader_recompiler/frontend/ir/modifiers.h1
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp2
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp6
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp4
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch.cpp1
5 files changed, 9 insertions, 5 deletions
diff --git a/src/shader_recompiler/frontend/ir/modifiers.h b/src/shader_recompiler/frontend/ir/modifiers.h
index 69035d462..1e9e8c8f5 100644
--- a/src/shader_recompiler/frontend/ir/modifiers.h
+++ b/src/shader_recompiler/frontend/ir/modifiers.h
@@ -42,6 +42,7 @@ union TextureInstInfo {
42 BitField<23, 2, u32> gather_component; 42 BitField<23, 2, u32> gather_component;
43 BitField<25, 2, u32> num_derivates; 43 BitField<25, 2, u32> num_derivates;
44 BitField<27, 3, ImageFormat> image_format; 44 BitField<27, 3, ImageFormat> image_format;
45 BitField<30, 1, u32> ndv_is_active;
45}; 46};
46static_assert(sizeof(TextureInstInfo) <= sizeof(u32)); 47static_assert(sizeof(TextureInstInfo) <= sizeof(u32));
47 48
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp
index ef4ffa54b..f00e20023 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/floating_point_swizzled_add.cpp
@@ -19,7 +19,7 @@ void TranslatorVisitor::FSWZADD(u64 insn) {
19 } const fswzadd{insn}; 19 } const fswzadd{insn};
20 20
21 if (fswzadd.ndv != 0) { 21 if (fswzadd.ndv != 0) {
22 throw NotImplementedException("FSWZADD NDV"); 22 LOG_WARNING(Shader, "(STUBBED) FSWZADD - NDV mode");
23 } 23 }
24 24
25 const IR::F32 src_a{GetFloatReg8(insn)}; 25 const IR::F32 src_a{GetFloatReg8(insn)};
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
index 82aec3b73..1ddfeab06 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
@@ -16,8 +16,10 @@ void MOV(TranslatorVisitor& v, u64 insn, const IR::U32& src, bool is_mov32i = fa
16 BitField<12, 4, u64> mov32i_mask; 16 BitField<12, 4, u64> mov32i_mask;
17 } const mov{insn}; 17 } const mov{insn};
18 18
19 if ((is_mov32i ? mov.mov32i_mask : mov.mask) != 0xf) { 19 u64 mask = is_mov32i ? mov.mov32i_mask : mov.mask;
20 throw NotImplementedException("Non-full move mask"); 20 if (mask != 0xf && mask != 0x1) {
21 LOG_WARNING(Shader, "(STUBBED) Masked Mov");
22 return;
21 } 23 }
22 v.X(mov.dest_reg, src); 24 v.X(mov.dest_reg, src);
23} 25}
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
index 2f930f1ea..6203003b3 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
@@ -209,7 +209,7 @@ void TranslatorVisitor::R2B(u64) {
209} 209}
210 210
211void TranslatorVisitor::RAM(u64) { 211void TranslatorVisitor::RAM(u64) {
212 ThrowNotImplemented(Opcode::RAM); 212 LOG_WARNING(Shader, "(STUBBED) RAM Instruction");
213} 213}
214 214
215void TranslatorVisitor::RET(u64) { 215void TranslatorVisitor::RET(u64) {
@@ -221,7 +221,7 @@ void TranslatorVisitor::RTT(u64) {
221} 221}
222 222
223void TranslatorVisitor::SAM(u64) { 223void TranslatorVisitor::SAM(u64) {
224 ThrowNotImplemented(Opcode::SAM); 224 LOG_WARNING(Shader, "(STUBBED) SAM Instruction");
225} 225}
226 226
227void TranslatorVisitor::SETCRSPTR(u64) { 227void TranslatorVisitor::SETCRSPTR(u64) {
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch.cpp
index 2459fc30d..7a9b7fff8 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/texture_fetch.cpp
@@ -172,6 +172,7 @@ void Impl(TranslatorVisitor& v, u64 insn, bool aoffi, Blod blod, bool lc,
172 info.is_depth.Assign(tex.dc != 0 ? 1 : 0); 172 info.is_depth.Assign(tex.dc != 0 ? 1 : 0);
173 info.has_bias.Assign(blod == Blod::LB || blod == Blod::LBA ? 1 : 0); 173 info.has_bias.Assign(blod == Blod::LB || blod == Blod::LBA ? 1 : 0);
174 info.has_lod_clamp.Assign(lc ? 1 : 0); 174 info.has_lod_clamp.Assign(lc ? 1 : 0);
175 info.ndv_is_active.Assign(tex.ndv != 0 ? 1 : 0);
175 176
176 const IR::Value sample{[&]() -> IR::Value { 177 const IR::Value sample{[&]() -> IR::Value {
177 if (tex.dc == 0) { 178 if (tex.dc == 0) {