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| author | 2021-04-11 19:16:12 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:27 -0400 | |
| commit | 5c61e860e4f83524ffce10ca447398e83de81640 (patch) | |
| tree | ff19c70e70170715c1de763d9674bf35d4aa5c42 /src/shader_recompiler/frontend | |
| parent | shader: Apply sign bit in FCMP (imm) (diff) | |
| download | yuzu-5c61e860e4f83524ffce10ca447398e83de81640.tar.gz yuzu-5c61e860e4f83524ffce10ca447398e83de81640.tar.xz yuzu-5c61e860e4f83524ffce10ca447398e83de81640.zip | |
shader: Implement SR_THREAD_KILL
Diffstat (limited to 'src/shader_recompiler/frontend')
4 files changed, 9 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp index a3339f624..54a273a92 100644 --- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp +++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp | |||
| @@ -347,6 +347,10 @@ U32 IREmitter::LocalInvocationIdZ() { | |||
| 347 | return U32{CompositeExtract(Inst(Opcode::LocalInvocationId), 2)}; | 347 | return U32{CompositeExtract(Inst(Opcode::LocalInvocationId), 2)}; |
| 348 | } | 348 | } |
| 349 | 349 | ||
| 350 | U1 IREmitter::IsHelperInvocation() { | ||
| 351 | return Inst<U1>(Opcode::IsHelperInvocation); | ||
| 352 | } | ||
| 353 | |||
| 350 | U32 IREmitter::LaneId() { | 354 | U32 IREmitter::LaneId() { |
| 351 | return Inst<U32>(Opcode::LaneId); | 355 | return Inst<U32>(Opcode::LaneId); |
| 352 | } | 356 | } |
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h index f9cbf1304..d04224707 100644 --- a/src/shader_recompiler/frontend/ir/ir_emitter.h +++ b/src/shader_recompiler/frontend/ir/ir_emitter.h | |||
| @@ -90,6 +90,8 @@ public: | |||
| 90 | [[nodiscard]] U32 LocalInvocationIdY(); | 90 | [[nodiscard]] U32 LocalInvocationIdY(); |
| 91 | [[nodiscard]] U32 LocalInvocationIdZ(); | 91 | [[nodiscard]] U32 LocalInvocationIdZ(); |
| 92 | 92 | ||
| 93 | [[nodiscard]] U1 IsHelperInvocation(); | ||
| 94 | |||
| 93 | [[nodiscard]] U32 LaneId(); | 95 | [[nodiscard]] U32 LaneId(); |
| 94 | 96 | ||
| 95 | [[nodiscard]] U32 LoadGlobalU8(const U64& address); | 97 | [[nodiscard]] U32 LoadGlobalU8(const U64& address); |
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc index dc776a73e..f70008682 100644 --- a/src/shader_recompiler/frontend/ir/opcodes.inc +++ b/src/shader_recompiler/frontend/ir/opcodes.inc | |||
| @@ -58,6 +58,7 @@ OPCODE(SetCFlag, Void, U1, | |||
| 58 | OPCODE(SetOFlag, Void, U1, ) | 58 | OPCODE(SetOFlag, Void, U1, ) |
| 59 | OPCODE(WorkgroupId, U32x3, ) | 59 | OPCODE(WorkgroupId, U32x3, ) |
| 60 | OPCODE(LocalInvocationId, U32x3, ) | 60 | OPCODE(LocalInvocationId, U32x3, ) |
| 61 | OPCODE(IsHelperInvocation, U1, ) | ||
| 61 | 62 | ||
| 62 | // Undefined | 63 | // Undefined |
| 63 | OPCODE(UndefU1, U1, ) | 64 | OPCODE(UndefU1, U1, ) |
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp index be1f21e7b..50650cc56 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp | |||
| @@ -113,6 +113,8 @@ enum class SpecialRegister : u64 { | |||
| 113 | 113 | ||
| 114 | [[nodiscard]] IR::U32 Read(IR::IREmitter& ir, SpecialRegister special_register) { | 114 | [[nodiscard]] IR::U32 Read(IR::IREmitter& ir, SpecialRegister special_register) { |
| 115 | switch (special_register) { | 115 | switch (special_register) { |
| 116 | case SpecialRegister::SR_THREAD_KILL: | ||
| 117 | return IR::U32{ir.Select(ir.IsHelperInvocation(), ir.Imm32(-1), ir.Imm32(0))}; | ||
| 116 | case SpecialRegister::SR_TID_X: | 118 | case SpecialRegister::SR_TID_X: |
| 117 | return ir.LocalInvocationIdX(); | 119 | return ir.LocalInvocationIdX(); |
| 118 | case SpecialRegister::SR_TID_Y: | 120 | case SpecialRegister::SR_TID_Y: |