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authorGravatar ReinUsesLisp2021-06-22 18:28:21 -0300
committerGravatar ameerj2021-07-22 21:51:39 -0400
commit4397053d5c848deae00d6599f91b1e5c137a9639 (patch)
tree65c858cc489eb5e30eecb14a6222e512ace5e4d8 /src/shader_recompiler/frontend
parentglsl: Fix IADD CC (diff)
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shader: Remove IAbs64
Diffstat (limited to 'src/shader_recompiler/frontend')
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.cpp11
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.h2
-rw-r--r--src/shader_recompiler/frontend/ir/opcodes.inc1
3 files changed, 3 insertions, 11 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index 2e75208e6..13159a68d 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -1152,15 +1152,8 @@ U32U64 IREmitter::INeg(const U32U64& value) {
1152 } 1152 }
1153} 1153}
1154 1154
1155U32U64 IREmitter::IAbs(const U32U64& value) { 1155U32 IREmitter::IAbs(const U32& value) {
1156 switch (value.Type()) { 1156 return Inst<U32>(Opcode::IAbs32, value);
1157 case Type::U32:
1158 return Inst<U32>(Opcode::IAbs32, value);
1159 case Type::U64:
1160 return Inst<U64>(Opcode::IAbs64, value);
1161 default:
1162 ThrowInvalidType(value.Type());
1163 }
1164} 1157}
1165 1158
1166U32U64 IREmitter::ShiftLeftLogical(const U32U64& base, const U32& shift) { 1159U32U64 IREmitter::ShiftLeftLogical(const U32U64& base, const U32& shift) {
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h
index bb3500c54..53f7b3b06 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.h
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.h
@@ -208,7 +208,7 @@ public:
208 [[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b); 208 [[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);
209 [[nodiscard]] U32 IMul(const U32& a, const U32& b); 209 [[nodiscard]] U32 IMul(const U32& a, const U32& b);
210 [[nodiscard]] U32U64 INeg(const U32U64& value); 210 [[nodiscard]] U32U64 INeg(const U32U64& value);
211 [[nodiscard]] U32U64 IAbs(const U32U64& value); 211 [[nodiscard]] U32 IAbs(const U32& value);
212 [[nodiscard]] U32U64 ShiftLeftLogical(const U32U64& base, const U32& shift); 212 [[nodiscard]] U32U64 ShiftLeftLogical(const U32U64& base, const U32& shift);
213 [[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift); 213 [[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift);
214 [[nodiscard]] U32U64 ShiftRightArithmetic(const U32U64& base, const U32& shift); 214 [[nodiscard]] U32U64 ShiftRightArithmetic(const U32U64& base, const U32& shift);
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc
index 8a8d0d759..9af750283 100644
--- a/src/shader_recompiler/frontend/ir/opcodes.inc
+++ b/src/shader_recompiler/frontend/ir/opcodes.inc
@@ -289,7 +289,6 @@ OPCODE(IMul32, U32, U32,
289OPCODE(INeg32, U32, U32, ) 289OPCODE(INeg32, U32, U32, )
290OPCODE(INeg64, U64, U64, ) 290OPCODE(INeg64, U64, U64, )
291OPCODE(IAbs32, U32, U32, ) 291OPCODE(IAbs32, U32, U32, )
292OPCODE(IAbs64, U64, U64, )
293OPCODE(ShiftLeftLogical32, U32, U32, U32, ) 292OPCODE(ShiftLeftLogical32, U32, U32, U32, )
294OPCODE(ShiftLeftLogical64, U64, U64, U32, ) 293OPCODE(ShiftLeftLogical64, U64, U64, U32, )
295OPCODE(ShiftRightLogical32, U32, U32, U32, ) 294OPCODE(ShiftRightLogical32, U32, U32, U32, )