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authorGravatar ReinUsesLisp2021-04-04 02:31:09 -0300
committerGravatar ameerj2021-07-22 21:51:26 -0400
commit3f594dd86bd1ee1b178109132482c7d6b43e66dd (patch)
tree7de68eba744644121f3409f2de8c2e7a0bd5c125 /src/shader_recompiler/frontend
parentvk_compute_pass: Fix compute passes (diff)
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shader: Reimplement GetCbufU64 as GetCbufU32x2
It may generate better code on some compilers and it's easier to handle.
Diffstat (limited to 'src/shader_recompiler/frontend')
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.cpp6
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.h4
-rw-r--r--src/shader_recompiler/frontend/ir/opcodes.inc2
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp12
4 files changed, 12 insertions, 12 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index dbfc670b0..dbd38a28b 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -162,8 +162,8 @@ U32 IREmitter::GetCbuf(const U32& binding, const U32& byte_offset) {
162 return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset); 162 return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset);
163} 163}
164 164
165UAny IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize, 165Value IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
166 bool is_signed) { 166 bool is_signed) {
167 switch (bitsize) { 167 switch (bitsize) {
168 case 8: 168 case 8:
169 return Inst<U32>(is_signed ? Opcode::GetCbufS8 : Opcode::GetCbufU8, binding, byte_offset); 169 return Inst<U32>(is_signed ? Opcode::GetCbufS8 : Opcode::GetCbufU8, binding, byte_offset);
@@ -172,7 +172,7 @@ UAny IREmitter::GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsi
172 case 32: 172 case 32:
173 return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset); 173 return Inst<U32>(Opcode::GetCbufU32, binding, byte_offset);
174 case 64: 174 case 64:
175 return Inst<U64>(Opcode::GetCbufU64, binding, byte_offset); 175 return Inst(Opcode::GetCbufU32x2, binding, byte_offset);
176 default: 176 default:
177 throw InvalidArgument("Invalid bit size {}", bitsize); 177 throw InvalidArgument("Invalid bit size {}", bitsize);
178 } 178 }
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h
index 14b743975..81a57fefe 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.h
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.h
@@ -56,8 +56,8 @@ public:
56 void SetIndirectBranchVariable(const U32& value); 56 void SetIndirectBranchVariable(const U32& value);
57 57
58 [[nodiscard]] U32 GetCbuf(const U32& binding, const U32& byte_offset); 58 [[nodiscard]] U32 GetCbuf(const U32& binding, const U32& byte_offset);
59 [[nodiscard]] UAny GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize, 59 [[nodiscard]] Value GetCbuf(const U32& binding, const U32& byte_offset, size_t bitsize,
60 bool is_signed); 60 bool is_signed);
61 [[nodiscard]] F32 GetFloatCbuf(const U32& binding, const U32& byte_offset); 61 [[nodiscard]] F32 GetFloatCbuf(const U32& binding, const U32& byte_offset);
62 62
63 [[nodiscard]] U1 GetZFlag(); 63 [[nodiscard]] U1 GetZFlag();
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc
index 3640a5d24..734f5328b 100644
--- a/src/shader_recompiler/frontend/ir/opcodes.inc
+++ b/src/shader_recompiler/frontend/ir/opcodes.inc
@@ -40,7 +40,7 @@ OPCODE(GetCbufU16, U32, U32,
40OPCODE(GetCbufS16, U32, U32, U32, ) 40OPCODE(GetCbufS16, U32, U32, U32, )
41OPCODE(GetCbufU32, U32, U32, U32, ) 41OPCODE(GetCbufU32, U32, U32, U32, )
42OPCODE(GetCbufF32, F32, U32, U32, ) 42OPCODE(GetCbufF32, F32, U32, U32, )
43OPCODE(GetCbufU64, U64, U32, U32, ) 43OPCODE(GetCbufU32x2, U32x2, U32, U32, )
44OPCODE(GetAttribute, F32, Attribute, ) 44OPCODE(GetAttribute, F32, Attribute, )
45OPCODE(SetAttribute, Void, Attribute, F32, ) 45OPCODE(SetAttribute, Void, Attribute, F32, )
46OPCODE(GetAttributeIndexed, F32, U32, ) 46OPCODE(GetAttributeIndexed, F32, U32, )
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp
index 49ccb7d62..ae3ecea32 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/load_constant.cpp
@@ -30,25 +30,25 @@ void TranslatorVisitor::LDC(u64 insn) {
30 const auto [index, offset]{Slot(ir, ldc.mode, imm_index, reg, imm)}; 30 const auto [index, offset]{Slot(ir, ldc.mode, imm_index, reg, imm)};
31 switch (ldc.size) { 31 switch (ldc.size) {
32 case Size::U8: 32 case Size::U8:
33 X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, false)); 33 X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 8, false)});
34 break; 34 break;
35 case Size::S8: 35 case Size::S8:
36 X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, true)); 36 X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 8, true)});
37 break; 37 break;
38 case Size::U16: 38 case Size::U16:
39 X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, false)); 39 X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 16, false)});
40 break; 40 break;
41 case Size::S16: 41 case Size::S16:
42 X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, true)); 42 X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 16, true)});
43 break; 43 break;
44 case Size::B32: 44 case Size::B32:
45 X(ldc.dest_reg, ir.GetCbuf(index, offset, 32, false)); 45 X(ldc.dest_reg, IR::U32{ir.GetCbuf(index, offset, 32, false)});
46 break; 46 break;
47 case Size::B64: { 47 case Size::B64: {
48 if (!IR::IsAligned(ldc.dest_reg, 2)) { 48 if (!IR::IsAligned(ldc.dest_reg, 2)) {
49 throw NotImplementedException("Unaligned destination register"); 49 throw NotImplementedException("Unaligned destination register");
50 } 50 }
51 const IR::Value vector{ir.UnpackUint2x32(ir.GetCbuf(index, offset, 64, false))}; 51 const IR::Value vector{ir.GetCbuf(index, offset, 64, false)};
52 for (int i = 0; i < 2; ++i) { 52 for (int i = 0; i < 2; ++i) {
53 X(ldc.dest_reg + i, IR::U32{ir.CompositeExtract(vector, i)}); 53 X(ldc.dest_reg + i, IR::U32{ir.CompositeExtract(vector, i)});
54 } 54 }