shader: Implement HADD2

6 files changed, 290 insertions, 23 deletions

diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index 0f1cab57a..186920d8f 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -334,12 +334,12 @@ Value IREmitter::CompositeConstruct(const Value& e1, const Value& e2, const Valu
 }
 
 Value IREmitter::CompositeExtract(const Value& vector, size_t element) {
-    const auto read = [&](Opcode opcode, size_t limit) -> Value {
+    const auto read{[&](Opcode opcode, size_t limit) -> Value {
         if (element >= limit) {
             throw InvalidArgument("Out of bounds element {}", element);
         }
         return Inst(opcode, vector, Value{static_cast<u32>(element)});
-    };
+    }};
     switch (vector.Type()) {
     case Type::U32x2:
         return read(Opcode::CompositeExtractU32x2, 2);
@@ -370,6 +370,43 @@ Value IREmitter::CompositeExtract(const Value& vector, size_t element) {
     }
 }
 
+Value IREmitter::CompositeInsert(const Value& vector, const Value& object, size_t element) {
+    const auto insert{[&](Opcode opcode, size_t limit) {
+        if (element >= limit) {
+            throw InvalidArgument("Out of bounds element {}", element);
+        }
+        return Inst(opcode, vector, object, Value{static_cast<u32>(element)});
+    }};
+    switch (vector.Type()) {
+    case Type::U32x2:
+        return insert(Opcode::CompositeInsertU32x2, 2);
+    case Type::U32x3:
+        return insert(Opcode::CompositeInsertU32x3, 3);
+    case Type::U32x4:
+        return insert(Opcode::CompositeInsertU32x4, 4);
+    case Type::F16x2:
+        return insert(Opcode::CompositeInsertF16x2, 2);
+    case Type::F16x3:
+        return insert(Opcode::CompositeInsertF16x3, 3);
+    case Type::F16x4:
+        return insert(Opcode::CompositeInsertF16x4, 4);
+    case Type::F32x2:
+        return insert(Opcode::CompositeInsertF32x2, 2);
+    case Type::F32x3:
+        return insert(Opcode::CompositeInsertF32x3, 3);
+    case Type::F32x4:
+        return insert(Opcode::CompositeInsertF32x4, 4);
+    case Type::F64x2:
+        return insert(Opcode::CompositeInsertF64x2, 2);
+    case Type::F64x3:
+        return insert(Opcode::CompositeInsertF64x3, 3);
+    case Type::F64x4:
+        return insert(Opcode::CompositeInsertF64x4, 4);
+    default:
+        ThrowInvalidType(vector.Type());
+    }
+}
+
 Value IREmitter::Select(const U1& condition, const Value& true_value, const Value& false_value) {
     if (true_value.Type() != false_value.Type()) {
         throw InvalidArgument("Mismatching types {} and {}", true_value.Type(), false_value.Type());
@@ -433,7 +470,7 @@ U32 IREmitter::PackFloat2x16(const Value& vector) {
 }
 
 Value IREmitter::UnpackFloat2x16(const U32& value) {
-    return Inst<Value>(Opcode::UnpackFloat2x16, value);
+    return Inst(Opcode::UnpackFloat2x16, value);
 }
 
 F64 IREmitter::PackDouble2x32(const Value& vector) {
@@ -968,7 +1005,7 @@ U32U64 IREmitter::ConvertFToI(size_t bitsize, bool is_signed, const F16F32F64& v
     }
 }
 
-U32U64 IREmitter::ConvertU(size_t result_bitsize, const U32U64& value) {
+U32U64 IREmitter::UConvert(size_t result_bitsize, const U32U64& value) {
     switch (result_bitsize) {
     case 32:
         switch (value.Type()) {
@@ -995,4 +1032,49 @@ U32U64 IREmitter::ConvertU(size_t result_bitsize, const U32U64& value) {
     throw NotImplementedException("Conversion from {} to {} bits", value.Type(), result_bitsize);
 }
 
+F16F32F64 IREmitter::FPConvert(size_t result_bitsize, const F16F32F64& value) {
+    switch (result_bitsize) {
+    case 16:
+        switch (value.Type()) {
+        case Type::F16:
+            // Nothing to do
+            return value;
+        case Type::F32:
+            return Inst<F16>(Opcode::ConvertF16F32, value);
+        case Type::F64:
+            throw LogicError("Illegal conversion from F64 to F16");
+        default:
+            break;
+        }
+        break;
+    case 32:
+        switch (value.Type()) {
+        case Type::F16:
+            return Inst<F32>(Opcode::ConvertF32F16, value);
+        case Type::F32:
+            // Nothing to do
+            return value;
+        case Type::F64:
+            return Inst<F64>(Opcode::ConvertF32F64, value);
+        default:
+            break;
+        }
+        break;
+    case 64:
+        switch (value.Type()) {
+        case Type::F16:
+            throw LogicError("Illegal conversion from F16 to F64");
+        case Type::F32:
+            // Nothing to do
+            return value;
+        case Type::F64:
+            return Inst<F64>(Opcode::ConvertF32F64, value);
+        default:
+            break;
+        }
+        break;
+    }
+    throw NotImplementedException("Conversion from {} to {} bits", value.Type(), result_bitsize);
+}
+
 } // namespace Shader::IR
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h
index 03a67985f..5beb99895 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.h
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.h
@@ -97,6 +97,7 @@ public:
     [[nodiscard]] Value CompositeConstruct(const Value& e1, const Value& e2, const Value& e3,
                                            const Value& e4);
     [[nodiscard]] Value CompositeExtract(const Value& vector, size_t element);
+    [[nodiscard]] Value CompositeInsert(const Value& vector, const Value& object, size_t element);
 
     [[nodiscard]] Value Select(const U1& condition, const Value& true_value,
                                const Value& false_value);
@@ -186,7 +187,8 @@ public:
     [[nodiscard]] U32U64 ConvertFToU(size_t bitsize, const F16F32F64& value);
     [[nodiscard]] U32U64 ConvertFToI(size_t bitsize, bool is_signed, const F16F32F64& value);
 
-    [[nodiscard]] U32U64 ConvertU(size_t result_bitsize, const U32U64& value);
+    [[nodiscard]] U32U64 UConvert(size_t result_bitsize, const U32U64& value);
+    [[nodiscard]] F16F32F64 FPConvert(size_t result_bitsize, const F16F32F64& value);
 
 private:
     IR::Block::iterator insertion_point;
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc
index aedbc5c3e..acfc0a829 100644
--- a/src/shader_recompiler/frontend/ir/opcodes.inc
+++ b/src/shader_recompiler/frontend/ir/opcodes.inc
@@ -83,24 +83,36 @@ OPCODE(CompositeConstructU32x4,                             U32x4,          U32,
 OPCODE(CompositeExtractU32x2,                               U32,            U32x2,          U32,                                            )
 OPCODE(CompositeExtractU32x3,                               U32,            U32x3,          U32,                                            )
 OPCODE(CompositeExtractU32x4,                               U32,            U32x4,          U32,                                            )
+OPCODE(CompositeInsertU32x2,                                U32x2,          U32x2,          U32,            U32,                            )
+OPCODE(CompositeInsertU32x3,                                U32x3,          U32x3,          U32,            U32,                            )
+OPCODE(CompositeInsertU32x4,                                U32x4,          U32x4,          U32,            U32,                            )
 OPCODE(CompositeConstructF16x2,                             F16x2,          F16,            F16,                                            )
 OPCODE(CompositeConstructF16x3,                             F16x3,          F16,            F16,            F16,                            )
 OPCODE(CompositeConstructF16x4,                             F16x4,          F16,            F16,            F16,            F16,            )
 OPCODE(CompositeExtractF16x2,                               F16,            F16x2,          U32,                                            )
 OPCODE(CompositeExtractF16x3,                               F16,            F16x3,          U32,                                            )
 OPCODE(CompositeExtractF16x4,                               F16,            F16x4,          U32,                                            )
+OPCODE(CompositeInsertF16x2,                                F16x2,          F16x2,          F16,            U32,                            )
+OPCODE(CompositeInsertF16x3,                                F16x3,          F16x3,          F16,            U32,                            )
+OPCODE(CompositeInsertF16x4,                                F16x4,          F16x4,          F16,            U32,                            )
 OPCODE(CompositeConstructF32x2,                             F32x2,          F32,            F32,                                            )
 OPCODE(CompositeConstructF32x3,                             F32x3,          F32,            F32,            F32,                            )
 OPCODE(CompositeConstructF32x4,                             F32x4,          F32,            F32,            F32,            F32,            )
 OPCODE(CompositeExtractF32x2,                               F32,            F32x2,          U32,                                            )
 OPCODE(CompositeExtractF32x3,                               F32,            F32x3,          U32,                                            )
 OPCODE(CompositeExtractF32x4,                               F32,            F32x4,          U32,                                            )
+OPCODE(CompositeInsertF32x2,                                F32x2,          F32x2,          F32,            U32,                            )
+OPCODE(CompositeInsertF32x3,                                F32x3,          F32x3,          F32,            U32,                            )
+OPCODE(CompositeInsertF32x4,                                F32x4,          F32x4,          F32,            U32,                            )
 OPCODE(CompositeConstructF64x2,                             F64x2,          F64,            F64,                                            )
 OPCODE(CompositeConstructF64x3,                             F64x3,          F64,            F64,            F64,                            )
 OPCODE(CompositeConstructF64x4,                             F64x4,          F64,            F64,            F64,            F64,            )
 OPCODE(CompositeExtractF64x2,                               F64,            F64x2,          U32,                                            )
 OPCODE(CompositeExtractF64x3,                               F64,            F64x3,          U32,                                            )
 OPCODE(CompositeExtractF64x4,                               F64,            F64x4,          U32,                                            )
+OPCODE(CompositeInsertF64x2,                                F64x2,          F64x2,          F64,            U32,                            )
+OPCODE(CompositeInsertF64x3,                                F64x3,          F64x3,          F64,            U32,                            )
+OPCODE(CompositeInsertF64x4,                                F64x4,          F64x4,          F64,            U32,                            )
 
 // Select operations
 OPCODE(SelectU8,                                            U8,             U1,             U8,             U8,                             )
@@ -277,6 +289,9 @@ OPCODE(ConvertU32F64,                                       U32,            F64,
 OPCODE(ConvertU64F16,                                       U64,            F16,                                                            )
 OPCODE(ConvertU64F32,                                       U64,            F32,                                                            )
 OPCODE(ConvertU64F64,                                       U64,            F64,                                                            )
-
 OPCODE(ConvertU64U32,                                       U64,            U32,                                                            )
 OPCODE(ConvertU32U64,                                       U32,            U64,                                                            )
+OPCODE(ConvertF16F32,                                       F16,            F32,                                                            )
+OPCODE(ConvertF32F16,                                       F32,            F16,                                                            )
+OPCODE(ConvertF32F64,                                       F32,            F64,                                                            )
+OPCODE(ConvertF64F32,                                       F64,            F32,                                                            )
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_add.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_add.cpp
new file mode 100644
index 000000000..6965adfb3
--- /dev/null
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/half_floating_point_add.cpp
@@ -0,0 +1,184 @@
+// Copyright 2021 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/common_types.h"
+#include "shader_recompiler/exception.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/common_encoding.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
+
+namespace Shader::Maxwell {
+namespace {
+enum class Merge : u64 {
+    H1_H0,
+    F32,
+    MRG_H0,
+    MRG_H1,
+};
+
+enum class Swizzle : u64 {
+    H1_H0,
+    F32,
+    H0_H0,
+    H1_H1,
+};
+
+std::pair<IR::F16F32F64, IR::F16F32F64> Extract(IR::IREmitter& ir, IR::U32 value, Swizzle swizzle) {
+    switch (swizzle) {
+    case Swizzle::H1_H0: {
+        const IR::Value vector{ir.UnpackFloat2x16(value)};
+        return {IR::F16{ir.CompositeExtract(vector, 0)}, IR::F16{ir.CompositeExtract(vector, 1)}};
+    }
+    case Swizzle::H0_H0: {
+        const IR::F16 scalar{ir.CompositeExtract(ir.UnpackFloat2x16(value), 0)};
+        return {scalar, scalar};
+    }
+    case Swizzle::H1_H1: {
+        const IR::F16 scalar{ir.CompositeExtract(ir.UnpackFloat2x16(value), 1)};
+        return {scalar, scalar};
+    }
+    case Swizzle::F32: {
+        const IR::F32 scalar{ir.BitCast<IR::F32>(value)};
+        return {scalar, scalar};
+    }
+    }
+    throw InvalidArgument("Invalid swizzle {}", swizzle);
+}
+
+IR::U32 MergeResult(IR::IREmitter& ir, IR::Reg dest, const IR::F16& lhs, const IR::F16& rhs,
+                    Merge merge) {
+    switch (merge) {
+    case Merge::H1_H0:
+        return ir.PackFloat2x16(ir.CompositeConstruct(lhs, rhs));
+    case Merge::F32:
+        return ir.BitCast<IR::U32, IR::F32>(ir.FPConvert(32, lhs));
+    case Merge::MRG_H0:
+    case Merge::MRG_H1: {
+        const IR::Value vector{ir.UnpackFloat2x16(ir.GetReg(dest))};
+        const bool h0{merge == Merge::MRG_H0};
+        const IR::F16& insert{h0 ? lhs : rhs};
+        return ir.PackFloat2x16(ir.CompositeInsert(vector, insert, h0 ? 0 : 1));
+    }
+    }
+    throw InvalidArgument("Invalid merge {}", merge);
+}
+
+void HADD2(TranslatorVisitor& v, u64 insn, Merge merge, bool ftz, bool sat, bool abs_a, bool neg_a,
+           Swizzle swizzle_a, bool abs_b, bool neg_b, Swizzle swizzle_b, const IR::U32& src_b) {
+    union {
+        u64 raw;
+        BitField<0, 8, IR::Reg> dest_reg;
+        BitField<8, 8, IR::Reg> src_a;
+    } const hadd2{insn};
+
+    auto [lhs_a, rhs_a]{Extract(v.ir, v.X(hadd2.src_a), swizzle_a)};
+    auto [lhs_b, rhs_b]{Extract(v.ir, src_b, swizzle_b)};
+    const bool promotion{lhs_a.Type() != lhs_b.Type()};
+    if (promotion) {
+        if (lhs_a.Type() == IR::Type::F16) {
+            lhs_a = v.ir.FPConvert(32, lhs_a);
+            rhs_a = v.ir.FPConvert(32, rhs_a);
+        }
+        if (lhs_b.Type() == IR::Type::F16) {
+            lhs_b = v.ir.FPConvert(32, lhs_b);
+            rhs_b = v.ir.FPConvert(32, rhs_b);
+        }
+    }
+    lhs_a = v.ir.FPAbsNeg(lhs_a, abs_a, neg_a);
+    rhs_a = v.ir.FPAbsNeg(rhs_a, abs_a, neg_a);
+
+    lhs_b = v.ir.FPAbsNeg(lhs_b, abs_b, neg_b);
+    rhs_b = v.ir.FPAbsNeg(rhs_b, abs_b, neg_b);
+
+    const IR::FpControl fp_control{
+        .no_contraction{true},
+        .rounding{IR::FpRounding::DontCare},
+        .fmz_mode{ftz ? IR::FmzMode::FTZ : IR::FmzMode::None},
+    };
+    IR::F16F32F64 lhs{v.ir.FPAdd(lhs_a, lhs_b, fp_control)};
+    IR::F16F32F64 rhs{v.ir.FPAdd(rhs_a, rhs_b, fp_control)};
+    if (sat) {
+        lhs = v.ir.FPSaturate(lhs);
+        rhs = v.ir.FPSaturate(rhs);
+    }
+    if (promotion) {
+        lhs = v.ir.FPConvert(16, lhs);
+        rhs = v.ir.FPConvert(16, rhs);
+    }
+    v.X(hadd2.dest_reg, MergeResult(v.ir, hadd2.dest_reg, lhs, rhs, merge));
+}
+} // Anonymous namespace
+
+void TranslatorVisitor::HADD2_reg(u64 insn) {
+    union {
+        u64 raw;
+        BitField<49, 2, Merge> merge;
+        BitField<39, 1, u64> ftz;
+        BitField<32, 1, u64> sat;
+        BitField<43, 1, u64> neg_a;
+        BitField<44, 1, u64> abs_a;
+        BitField<47, 2, Swizzle> swizzle_a;
+        BitField<31, 1, u64> neg_b;
+        BitField<30, 1, u64> abs_b;
+        BitField<28, 2, Swizzle> swizzle_b;
+    } const hadd2{insn};
+
+    HADD2(*this, insn, hadd2.merge, hadd2.ftz != 0, hadd2.sat != 0, hadd2.abs_a != 0,
+          hadd2.neg_a != 0, hadd2.swizzle_a, hadd2.abs_b != 0, hadd2.neg_b != 0, hadd2.swizzle_b,
+          GetReg20(insn));
+}
+
+void TranslatorVisitor::HADD2_cbuf(u64 insn) {
+    union {
+        u64 raw;
+        BitField<49, 2, Merge> merge;
+        BitField<39, 1, u64> ftz;
+        BitField<52, 1, u64> sat;
+        BitField<43, 1, u64> neg_a;
+        BitField<44, 1, u64> abs_a;
+        BitField<47, 2, Swizzle> swizzle_a;
+        BitField<56, 1, u64> neg_b;
+        BitField<54, 1, u64> abs_b;
+    } const hadd2{insn};
+
+    HADD2(*this, insn, hadd2.merge, hadd2.ftz != 0, hadd2.sat != 0, hadd2.abs_a != 0,
+          hadd2.neg_a != 0, hadd2.swizzle_a, hadd2.abs_b != 0, hadd2.neg_b != 0, Swizzle::F32,
+          GetCbuf(insn));
+}
+
+void TranslatorVisitor::HADD2_imm(u64 insn) {
+    union {
+        u64 raw;
+        BitField<49, 2, Merge> merge;
+        BitField<39, 1, u64> ftz;
+        BitField<52, 1, u64> sat;
+        BitField<43, 1, u64> neg_a;
+        BitField<44, 1, u64> abs_a;
+        BitField<47, 2, Swizzle> swizzle_a;
+        BitField<56, 1, u64> neg_high;
+        BitField<30, 9, u64> high;
+        BitField<29, 1, u64> neg_low;
+        BitField<20, 9, u64> low;
+    } const hadd2{insn};
+
+    const u32 imm{static_cast<u32>(hadd2.low << 6) | ((hadd2.neg_low != 0 ? 1 : 0) << 15) |
+                  static_cast<u32>(hadd2.high << 22) | ((hadd2.neg_high != 0 ? 1 : 0) << 31)};
+    HADD2(*this, insn, hadd2.merge, hadd2.ftz != 0, hadd2.sat != 0, hadd2.abs_a != 0,
+          hadd2.neg_a != 0, hadd2.swizzle_a, false, false, Swizzle::H1_H0, ir.Imm32(imm));
+}
+
+void TranslatorVisitor::HADD2_32I(u64 insn) {
+    union {
+        u64 raw;
+        BitField<55, 1, u64> ftz;
+        BitField<52, 1, u64> sat;
+        BitField<56, 1, u64> neg_a;
+        BitField<53, 2, Swizzle> swizzle_a;
+        BitField<20, 32, u64> imm32;
+    } const hadd2{insn};
+
+    const u32 imm{static_cast<u32>(hadd2.imm32)};
+    HADD2(*this, insn, Merge::H1_H0, hadd2.ftz != 0, hadd2.sat != 0, false, hadd2.neg_a != 0,
+          hadd2.swizzle_a, false, false, Swizzle::H1_H0, ir.Imm32(imm));
+}
+} // namespace Shader::Maxwell
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/load_store_memory.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/load_store_memory.cpp
index 727524284..748b856c9 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/load_store_memory.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/load_store_memory.cpp
@@ -59,7 +59,7 @@ IR::U64 Address(TranslatorVisitor& v, u64 insn) {
     const IR::U64 address{[&]() -> IR::U64 {
         if (mem.e == 0) {
             // LDG/STG without .E uses a 32-bit pointer, zero-extend it
-            return v.ir.ConvertU(64, v.X(mem.addr_reg));
+            return v.ir.UConvert(64, v.X(mem.addr_reg));
         }
         if (!IR::IsAligned(mem.addr_reg, 2)) {
             throw NotImplementedException("Unaligned address register");
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
index a0535f1c2..c24f29ff7 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
@@ -265,22 +265,6 @@ void TranslatorVisitor::GETLMEMBASE(u64) {
     ThrowNotImplemented(Opcode::GETLMEMBASE);
 }
 
-void TranslatorVisitor::HADD2_reg(u64) {
-    ThrowNotImplemented(Opcode::HADD2_reg);
-}
-
-void TranslatorVisitor::HADD2_cbuf(u64) {
-    ThrowNotImplemented(Opcode::HADD2_cbuf);
-}
-
-void TranslatorVisitor::HADD2_imm(u64) {
-    ThrowNotImplemented(Opcode::HADD2_imm);
-}
-
-void TranslatorVisitor::HADD2_32I(u64) {
-    ThrowNotImplemented(Opcode::HADD2_32I);
-}
-
 void TranslatorVisitor::HFMA2_reg(u64) {
     ThrowNotImplemented(Opcode::HFMA2_reg);
 }