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| author |  FengChen | 2022-10-30 19:59:11 +0800 |
|---|---|---|
| committer | Feng Chen | 2022-11-07 15:42:42 +0800 |
| commit | a4472b55260ed1ccbad0d191d11abd2330145140 (patch) | |
| tree | ed58bca8f35b79497099c8c73675332be455c28e /src/shader_recompiler/frontend/maxwell | |
| parent | Merge pull request #9163 from vonchenplus/draw_error (diff) | |
| download | yuzu-a4472b55260ed1ccbad0d191d11abd2330145140.tar.gz yuzu-a4472b55260ed1ccbad0d191d11abd2330145140.tar.xz yuzu-a4472b55260ed1ccbad0d191d11abd2330145140.zip | |
video_core: Fix few issues in Tess stage
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp index 52be12f9c..753c62098 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp | |||
| @@ -117,8 +117,7 @@ enum class SpecialRegister : u64 { | |||
| 117 | case SpecialRegister::SR_THREAD_KILL: | 117 | case SpecialRegister::SR_THREAD_KILL: |
| 118 | return IR::U32{ir.Select(ir.IsHelperInvocation(), ir.Imm32(-1), ir.Imm32(0))}; | 118 | return IR::U32{ir.Select(ir.IsHelperInvocation(), ir.Imm32(-1), ir.Imm32(0))}; |
| 119 | case SpecialRegister::SR_INVOCATION_INFO: | 119 | case SpecialRegister::SR_INVOCATION_INFO: |
| 120 | LOG_WARNING(Shader, "(STUBBED) SR_INVOCATION_INFO"); | 120 | return ir.InvocationInfo(); |
| 121 | return ir.Imm32(0x00ff'0000); | ||
| 122 | case SpecialRegister::SR_TID: { | 121 | case SpecialRegister::SR_TID: { |
| 123 | const IR::Value tid{ir.LocalInvocationId()}; | 122 | const IR::Value tid{ir.LocalInvocationId()}; |
| 124 | return ir.BitFieldInsert(ir.BitFieldInsert(IR::U32{ir.CompositeExtract(tid, 0)}, | 123 | return ir.BitFieldInsert(ir.BitFieldInsert(IR::U32{ir.CompositeExtract(tid, 0)}, |