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authorGravatar ReinUsesLisp2021-04-11 19:16:12 -0300
committerGravatar ameerj2021-07-22 21:51:27 -0400
commit5c61e860e4f83524ffce10ca447398e83de81640 (patch)
treeff19c70e70170715c1de763d9674bf35d4aa5c42 /src/shader_recompiler/frontend/maxwell
parentshader: Apply sign bit in FCMP (imm) (diff)
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shader: Implement SR_THREAD_KILL
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell')
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
index be1f21e7b..50650cc56 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_special_register.cpp
@@ -113,6 +113,8 @@ enum class SpecialRegister : u64 {
113 113
114[[nodiscard]] IR::U32 Read(IR::IREmitter& ir, SpecialRegister special_register) { 114[[nodiscard]] IR::U32 Read(IR::IREmitter& ir, SpecialRegister special_register) {
115 switch (special_register) { 115 switch (special_register) {
116 case SpecialRegister::SR_THREAD_KILL:
117 return IR::U32{ir.Select(ir.IsHelperInvocation(), ir.Imm32(-1), ir.Imm32(0))};
116 case SpecialRegister::SR_TID_X: 118 case SpecialRegister::SR_TID_X:
117 return ir.LocalInvocationIdX(); 119 return ir.LocalInvocationIdX();
118 case SpecialRegister::SR_TID_Y: 120 case SpecialRegister::SR_TID_Y: