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authorGravatar ameerj2021-03-01 15:58:16 -0500
committerGravatar ameerj2021-07-22 21:51:23 -0400
commit103b9da4f7115ff47eee52d0dbd31b5b7a18b257 (patch)
tree52e00b1766326559fad61cefa460b6666d2792c9 /src/shader_recompiler/frontend/maxwell/translate
parentshader: Implement ISET, add common_funcs (diff)
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shader: Implement FLO
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate')
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp46
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp12
2 files changed, 46 insertions, 12 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp
new file mode 100644
index 000000000..d5361bec5
--- /dev/null
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/find_leading_one.cpp
@@ -0,0 +1,46 @@
1// Copyright 2021 yuzu Emulator Project
2// Licensed under GPLv2 or any later version
3// Refer to the license.txt file included.
4
5#include "common/bit_field.h"
6#include "common/common_types.h"
7#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
8
9namespace Shader::Maxwell {
10namespace {
11void FLO(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
12 union {
13 u64 insn;
14 BitField<0, 8, IR::Reg> dest_reg;
15 BitField<40, 1, u64> tilde;
16 BitField<41, 1, u64> shift;
17 BitField<48, 1, u64> is_signed;
18 } const flo{insn};
19
20 const bool invert{flo.tilde != 0};
21 const bool is_signed{flo.is_signed != 0};
22 const bool shift_op{flo.shift != 0};
23
24 const IR::U32 operand{invert ? v.ir.BitwiseNot(src) : src};
25 const IR::U32 find_result{is_signed ? v.ir.FindSMsb(operand) : v.ir.FindUMsb(operand)};
26 const IR::U1 find_fail{v.ir.IEqual(find_result, v.ir.Imm32(-1))};
27 const IR::U32 offset{v.ir.Imm32(31)};
28 const IR::U32 success_result{shift_op ? IR::U32{v.ir.ISub(offset, find_result)} : find_result};
29
30 const IR::U32 result{v.ir.Select(find_fail, find_result, success_result)};
31 v.X(flo.dest_reg, result);
32}
33} // Anonymous namespace
34
35void TranslatorVisitor::FLO_reg(u64 insn) {
36 FLO(*this, insn, GetReg20(insn));
37}
38
39void TranslatorVisitor::FLO_cbuf(u64 insn) {
40 FLO(*this, insn, GetCbuf(insn));
41}
42
43void TranslatorVisitor::FLO_imm(u64 insn) {
44 FLO(*this, insn, GetImm20(insn));
45}
46} // namespace Shader::Maxwell
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
index f327e6fa5..2da0b87c4 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
@@ -217,18 +217,6 @@ void TranslatorVisitor::FCMP_imm(u64) {
217 ThrowNotImplemented(Opcode::FCMP_imm); 217 ThrowNotImplemented(Opcode::FCMP_imm);
218} 218}
219 219
220void TranslatorVisitor::FLO_reg(u64) {
221 ThrowNotImplemented(Opcode::FLO_reg);
222}
223
224void TranslatorVisitor::FLO_cbuf(u64) {
225 ThrowNotImplemented(Opcode::FLO_cbuf);
226}
227
228void TranslatorVisitor::FLO_imm(u64) {
229 ThrowNotImplemented(Opcode::FLO_imm);
230}
231
232void TranslatorVisitor::FMNMX_reg(u64) { 220void TranslatorVisitor::FMNMX_reg(u64) {
233 ThrowNotImplemented(Opcode::FMNMX_reg); 221 ThrowNotImplemented(Opcode::FMNMX_reg);
234} 222}