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| author | 2021-02-22 22:59:16 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:22 -0400 | |
| commit | e44752ddc8804961eb84f8c225bb36d5b4c77bc1 (patch) | |
| tree | 84df0e38680470a0ee8c2230625193c4156ddea6 /src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |
| parent | shader: Fix MOV(reg), add SHL variants and emit neg and abs instructions (diff) | |
| download | yuzu-e44752ddc8804961eb84f8c225bb36d5b4c77bc1.tar.gz yuzu-e44752ddc8804961eb84f8c225bb36d5b4c77bc1.tar.xz yuzu-e44752ddc8804961eb84f8c225bb36d5b4c77bc1.zip | |
shader: FMUL, select, RRO, and MUFU fixes
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp index 165d475b9..a5a0e1a9b 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |||
| @@ -48,11 +48,11 @@ IR::U32 TranslatorVisitor::GetReg39(u64 insn) { | |||
| 48 | return X(reg.index); | 48 | return X(reg.index); |
| 49 | } | 49 | } |
| 50 | 50 | ||
| 51 | IR::F32 TranslatorVisitor::GetRegFloat20(u64 insn) { | 51 | IR::F32 TranslatorVisitor::GetFloatReg20(u64 insn) { |
| 52 | return ir.BitCast<IR::F32>(GetReg20(insn)); | 52 | return ir.BitCast<IR::F32>(GetReg20(insn)); |
| 53 | } | 53 | } |
| 54 | 54 | ||
| 55 | IR::F32 TranslatorVisitor::GetRegFloat39(u64 insn) { | 55 | IR::F32 TranslatorVisitor::GetFloatReg39(u64 insn) { |
| 56 | return ir.BitCast<IR::F32>(GetReg39(insn)); | 56 | return ir.BitCast<IR::F32>(GetReg39(insn)); |
| 57 | } | 57 | } |
| 58 | 58 | ||
| @@ -110,6 +110,14 @@ IR::U32 TranslatorVisitor::GetImm32(u64 insn) { | |||
| 110 | return ir.Imm32(static_cast<u32>(imm.value)); | 110 | return ir.Imm32(static_cast<u32>(imm.value)); |
| 111 | } | 111 | } |
| 112 | 112 | ||
| 113 | IR::F32 TranslatorVisitor::GetFloatImm32(u64 insn) { | ||
| 114 | union { | ||
| 115 | u64 raw; | ||
| 116 | BitField<20, 32, u64> value; | ||
| 117 | } const imm{insn}; | ||
| 118 | return ir.Imm32(Common::BitCast<f32>(static_cast<u32>(imm.value))); | ||
| 119 | } | ||
| 120 | |||
| 113 | void TranslatorVisitor::SetZFlag(const IR::U1& value) { | 121 | void TranslatorVisitor::SetZFlag(const IR::U1& value) { |
| 114 | ir.SetZFlag(value); | 122 | ir.SetZFlag(value); |
| 115 | } | 123 | } |