diff options
| author | 2021-02-03 16:43:04 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:21 -0400 | |
| commit | d24a16045f0f6b0b873d5e3b5bf187c1a8c4343f (patch) | |
| tree | 0108a028b437bc59dfe7864f333cf4c50a46d3b5 /src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |
| parent | shader: SSA and dominance (diff) | |
| download | yuzu-d24a16045f0f6b0b873d5e3b5bf187c1a8c4343f.tar.gz yuzu-d24a16045f0f6b0b873d5e3b5bf187c1a8c4343f.tar.xz yuzu-d24a16045f0f6b0b873d5e3b5bf187c1a8c4343f.zip | |
shader: Initial instruction support
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp index 7bc7ce9f2..548c7f611 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |||
| @@ -16,6 +16,22 @@ void TranslatorVisitor::X(IR::Reg dest_reg, const IR::U32& value) { | |||
| 16 | ir.SetReg(dest_reg, value); | 16 | ir.SetReg(dest_reg, value); |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | IR::U32 TranslatorVisitor::GetReg20(u64 insn) { | ||
| 20 | union { | ||
| 21 | u64 raw; | ||
| 22 | BitField<20, 8, IR::Reg> index; | ||
| 23 | } const reg{insn}; | ||
| 24 | return X(reg.index); | ||
| 25 | } | ||
| 26 | |||
| 27 | IR::U32 TranslatorVisitor::GetReg39(u64 insn) { | ||
| 28 | union { | ||
| 29 | u64 raw; | ||
| 30 | BitField<39, 8, IR::Reg> index; | ||
| 31 | } const reg{insn}; | ||
| 32 | return X(reg.index); | ||
| 33 | } | ||
| 34 | |||
| 19 | IR::U32 TranslatorVisitor::GetCbuf(u64 insn) { | 35 | IR::U32 TranslatorVisitor::GetCbuf(u64 insn) { |
| 20 | union { | 36 | union { |
| 21 | u64 raw; | 37 | u64 raw; |
| @@ -33,7 +49,7 @@ IR::U32 TranslatorVisitor::GetCbuf(u64 insn) { | |||
| 33 | return ir.GetCbuf(binding, byte_offset); | 49 | return ir.GetCbuf(binding, byte_offset); |
| 34 | } | 50 | } |
| 35 | 51 | ||
| 36 | IR::U32 TranslatorVisitor::GetImm(u64 insn) { | 52 | IR::U32 TranslatorVisitor::GetImm20(u64 insn) { |
| 37 | union { | 53 | union { |
| 38 | u64 raw; | 54 | u64 raw; |
| 39 | BitField<20, 19, u64> value; | 55 | BitField<20, 19, u64> value; |
| @@ -44,6 +60,14 @@ IR::U32 TranslatorVisitor::GetImm(u64 insn) { | |||
| 44 | return ir.Imm32(value); | 60 | return ir.Imm32(value); |
| 45 | } | 61 | } |
| 46 | 62 | ||
| 63 | IR::U32 TranslatorVisitor::GetImm32(u64 insn) { | ||
| 64 | union { | ||
| 65 | u64 raw; | ||
| 66 | BitField<20, 32, u64> value; | ||
| 67 | } const imm{insn}; | ||
| 68 | return ir.Imm32(static_cast<u32>(imm.value)); | ||
| 69 | } | ||
| 70 | |||
| 47 | void TranslatorVisitor::SetZFlag(const IR::U1& value) { | 71 | void TranslatorVisitor::SetZFlag(const IR::U1& value) { |
| 48 | ir.SetZFlag(value); | 72 | ir.SetZFlag(value); |
| 49 | } | 73 | } |