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authorGravatar ameerj2021-03-21 02:09:14 -0400
committerGravatar ameerj2021-07-22 21:51:24 -0400
commitc858b8ba97d3ff79dcff0795c1184ee356f2cd1a (patch)
treea6b0c12aebb276c8a475b206941779d8d1af371d /src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
parentshader: Add FP64 register load/store helpers (diff)
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shader: Implement DMUL and DFMA
Also add a missing const on DADD
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
index 2d2f6f9c6..758a0230a 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
@@ -90,6 +90,14 @@ IR::F64 TranslatorVisitor::GetDoubleReg20(u64 insn) {
90 return D(reg.index); 90 return D(reg.index);
91} 91}
92 92
93IR::F64 TranslatorVisitor::GetDoubleReg39(u64 insn) {
94 union {
95 u64 raw;
96 BitField<39, 8, IR::Reg> index;
97 } const reg{insn};
98 return D(reg.index);
99}
100
93static std::pair<IR::U32, IR::U32> CbufAddr(u64 insn) { 101static std::pair<IR::U32, IR::U32> CbufAddr(u64 insn) {
94 union { 102 union {
95 u64 raw; 103 u64 raw;