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| author | 2021-03-24 00:02:30 +0100 | |
|---|---|---|
| committer | 2021-07-22 21:51:24 -0400 | |
| commit | 8cb9443cb99c4510e6ef26a91d09a31a8fa6281f (patch) | |
| tree | 2337f294c7179e1e2e98cafedde5c2eb254965cb /src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |
| parent | shader: Implement NDC [-1, 1], attribute types and default varying initializa... (diff) | |
| download | yuzu-8cb9443cb99c4510e6ef26a91d09a31a8fa6281f.tar.gz yuzu-8cb9443cb99c4510e6ef26a91d09a31a8fa6281f.tar.xz yuzu-8cb9443cb99c4510e6ef26a91d09a31a8fa6281f.zip | |
shader: Fix F2I
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp index 758a0230a..9bae89c10 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |||
| @@ -21,6 +21,13 @@ IR::U32 TranslatorVisitor::X(IR::Reg reg) { | |||
| 21 | return ir.GetReg(reg); | 21 | return ir.GetReg(reg); |
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | IR::U64 TranslatorVisitor::L(IR::Reg reg) { | ||
| 25 | if (!IR::IsAligned(reg, 2)) { | ||
| 26 | throw NotImplementedException("Unaligned source register {}", reg); | ||
| 27 | } | ||
| 28 | return IR::U64{ir.PackUint2x32(ir.CompositeConstruct(X(reg), X(reg + 1)))}; | ||
| 29 | } | ||
| 30 | |||
| 24 | IR::F32 TranslatorVisitor::F(IR::Reg reg) { | 31 | IR::F32 TranslatorVisitor::F(IR::Reg reg) { |
| 25 | return ir.BitCast<IR::F32>(X(reg)); | 32 | return ir.BitCast<IR::F32>(X(reg)); |
| 26 | } | 33 | } |
| @@ -36,6 +43,16 @@ void TranslatorVisitor::X(IR::Reg dest_reg, const IR::U32& value) { | |||
| 36 | ir.SetReg(dest_reg, value); | 43 | ir.SetReg(dest_reg, value); |
| 37 | } | 44 | } |
| 38 | 45 | ||
| 46 | void TranslatorVisitor::L(IR::Reg dest_reg, const IR::U64& value) { | ||
| 47 | if (!IR::IsAligned(dest_reg, 2)) { | ||
| 48 | throw NotImplementedException("Unaligned destination register {}", dest_reg); | ||
| 49 | } | ||
| 50 | const IR::Value result{ir.UnpackUint2x32(value)}; | ||
| 51 | for (int i = 0; i < 2; i++) { | ||
| 52 | X(dest_reg + i, IR::U32{ir.CompositeExtract(result, i)}); | ||
| 53 | } | ||
| 54 | } | ||
| 55 | |||
| 39 | void TranslatorVisitor::F(IR::Reg dest_reg, const IR::F32& value) { | 56 | void TranslatorVisitor::F(IR::Reg dest_reg, const IR::F32& value) { |
| 40 | X(dest_reg, ir.BitCast<IR::U32>(value)); | 57 | X(dest_reg, ir.BitCast<IR::U32>(value)); |
| 41 | } | 58 | } |