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| author | 2021-02-21 17:50:14 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:22 -0400 | |
| commit | 704c6f353f68745168902c6c66c04bb730bd30e6 (patch) | |
| tree | 71ed9654de41b5828ae2613167537d39499d2f3b /src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |
| parent | shader: Add denorm flush support (diff) | |
| download | yuzu-704c6f353f68745168902c6c66c04bb730bd30e6.tar.gz yuzu-704c6f353f68745168902c6c66c04bb730bd30e6.tar.xz yuzu-704c6f353f68745168902c6c66c04bb730bd30e6.zip | |
shader: Rename, implement FADD.SAT and P2R (imm)
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
| -rw-r--r-- | src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | 17 |
1 files changed, 14 insertions, 3 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp index 079e3497f..be17bb0d9 100644 --- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp +++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp | |||
| @@ -48,11 +48,11 @@ IR::U32 TranslatorVisitor::GetReg39(u64 insn) { | |||
| 48 | return X(reg.index); | 48 | return X(reg.index); |
| 49 | } | 49 | } |
| 50 | 50 | ||
| 51 | IR::F32 TranslatorVisitor::GetReg20F(u64 insn) { | 51 | IR::F32 TranslatorVisitor::GetRegFloat20(u64 insn) { |
| 52 | return ir.BitCast<IR::F32>(GetReg20(insn)); | 52 | return ir.BitCast<IR::F32>(GetReg20(insn)); |
| 53 | } | 53 | } |
| 54 | 54 | ||
| 55 | IR::F32 TranslatorVisitor::GetReg39F(u64 insn) { | 55 | IR::F32 TranslatorVisitor::GetRegFloat39(u64 insn) { |
| 56 | return ir.BitCast<IR::F32>(GetReg39(insn)); | 56 | return ir.BitCast<IR::F32>(GetReg39(insn)); |
| 57 | } | 57 | } |
| 58 | 58 | ||
| @@ -73,7 +73,7 @@ IR::U32 TranslatorVisitor::GetCbuf(u64 insn) { | |||
| 73 | return ir.GetCbuf(binding, byte_offset); | 73 | return ir.GetCbuf(binding, byte_offset); |
| 74 | } | 74 | } |
| 75 | 75 | ||
| 76 | IR::F32 TranslatorVisitor::GetCbufF(u64 insn) { | 76 | IR::F32 TranslatorVisitor::GetFloatCbuf(u64 insn) { |
| 77 | return ir.BitCast<IR::F32>(GetCbuf(insn)); | 77 | return ir.BitCast<IR::F32>(GetCbuf(insn)); |
| 78 | } | 78 | } |
| 79 | 79 | ||
| @@ -88,6 +88,17 @@ IR::U32 TranslatorVisitor::GetImm20(u64 insn) { | |||
| 88 | return ir.Imm32(value); | 88 | return ir.Imm32(value); |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | IR::F32 TranslatorVisitor::GetFloatImm20(u64 insn) { | ||
| 92 | union { | ||
| 93 | u64 raw; | ||
| 94 | BitField<20, 19, u64> value; | ||
| 95 | BitField<56, 1, u64> is_negative; | ||
| 96 | } const imm{insn}; | ||
| 97 | const f32 positive_value{Common::BitCast<f32>(static_cast<u32>(imm.value) << 12)}; | ||
| 98 | const f32 value{imm.is_negative != 0 ? -positive_value : positive_value}; | ||
| 99 | return ir.Imm32(value); | ||
| 100 | } | ||
| 101 | |||
| 91 | IR::U32 TranslatorVisitor::GetImm32(u64 insn) { | 102 | IR::U32 TranslatorVisitor::GetImm32(u64 insn) { |
| 92 | union { | 103 | union { |
| 93 | u64 raw; | 104 | u64 raw; |