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authorGravatar ameerj2021-03-28 22:23:45 -0400
committerGravatar ameerj2021-07-22 21:51:25 -0400
commit6c51f496320f698e123207c09ca61e55180a31b5 (patch)
treec5ecbbce29797fd7ba3138e11f9c364899375e2b /src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
parentshader: Implement BRX (diff)
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shader: Implement FSWZADD
Diffstat (limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp')
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
index 9bae89c10..30b570ce4 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/impl.cpp
@@ -91,6 +91,10 @@ IR::U32 TranslatorVisitor::GetReg39(u64 insn) {
91 return X(reg.index); 91 return X(reg.index);
92} 92}
93 93
94IR::F32 TranslatorVisitor::GetFloatReg8(u64 insn) {
95 return ir.BitCast<IR::F32>(GetReg8(insn));
96}
97
94IR::F32 TranslatorVisitor::GetFloatReg20(u64 insn) { 98IR::F32 TranslatorVisitor::GetFloatReg20(u64 insn) {
95 return ir.BitCast<IR::F32>(GetReg20(insn)); 99 return ir.BitCast<IR::F32>(GetReg20(insn));
96} 100}