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| author | 2021-03-07 14:48:03 -0500 | |
|---|---|---|
| committer | 2021-07-22 21:51:23 -0400 | |
| commit | 924f0a9149b6777782347be3d2c833a5f8e90058 (patch) | |
| tree | 1bd15a053df1f337410b9a9c95809c4095afa459 /src/shader_recompiler/frontend/ir | |
| parent | shader: Implement LEA (diff) | |
| download | yuzu-924f0a9149b6777782347be3d2c833a5f8e90058.tar.gz yuzu-924f0a9149b6777782347be3d2c833a5f8e90058.tar.xz yuzu-924f0a9149b6777782347be3d2c833a5f8e90058.zip | |
shader: Implement SHF
Diffstat (limited to 'src/shader_recompiler/frontend/ir')
| -rw-r--r-- | src/shader_recompiler/frontend/ir/ir_emitter.cpp | 22 | ||||
| -rw-r--r-- | src/shader_recompiler/frontend/ir/ir_emitter.h | 4 | ||||
| -rw-r--r-- | src/shader_recompiler/frontend/ir/opcodes.inc | 2 |
3 files changed, 22 insertions, 6 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp index 01f52183c..1659b7f3b 100644 --- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp +++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp | |||
| @@ -813,8 +813,15 @@ U32 IREmitter::IAbs(const U32& value) { | |||
| 813 | return Inst<U32>(Opcode::IAbs32, value); | 813 | return Inst<U32>(Opcode::IAbs32, value); |
| 814 | } | 814 | } |
| 815 | 815 | ||
| 816 | U32 IREmitter::ShiftLeftLogical(const U32& base, const U32& shift) { | 816 | U32U64 IREmitter::ShiftLeftLogical(const U32U64& base, const U32& shift) { |
| 817 | return Inst<U32>(Opcode::ShiftLeftLogical32, base, shift); | 817 | switch (base.Type()) { |
| 818 | case Type::U32: | ||
| 819 | return Inst<U32>(Opcode::ShiftLeftLogical32, base, shift); | ||
| 820 | case Type::U64: | ||
| 821 | return Inst<U64>(Opcode::ShiftLeftLogical64, base, shift); | ||
| 822 | default: | ||
| 823 | ThrowInvalidType(base.Type()); | ||
| 824 | } | ||
| 818 | } | 825 | } |
| 819 | 826 | ||
| 820 | U32U64 IREmitter::ShiftRightLogical(const U32U64& base, const U32& shift) { | 827 | U32U64 IREmitter::ShiftRightLogical(const U32U64& base, const U32& shift) { |
| @@ -828,8 +835,15 @@ U32U64 IREmitter::ShiftRightLogical(const U32U64& base, const U32& shift) { | |||
| 828 | } | 835 | } |
| 829 | } | 836 | } |
| 830 | 837 | ||
| 831 | U32 IREmitter::ShiftRightArithmetic(const U32& base, const U32& shift) { | 838 | U32U64 IREmitter::ShiftRightArithmetic(const U32U64& base, const U32& shift) { |
| 832 | return Inst<U32>(Opcode::ShiftRightArithmetic32, base, shift); | 839 | switch (base.Type()) { |
| 840 | case Type::U32: | ||
| 841 | return Inst<U32>(Opcode::ShiftRightArithmetic32, base, shift); | ||
| 842 | case Type::U64: | ||
| 843 | return Inst<U64>(Opcode::ShiftRightArithmetic64, base, shift); | ||
| 844 | default: | ||
| 845 | ThrowInvalidType(base.Type()); | ||
| 846 | } | ||
| 833 | } | 847 | } |
| 834 | 848 | ||
| 835 | U32 IREmitter::BitwiseAnd(const U32& a, const U32& b) { | 849 | U32 IREmitter::BitwiseAnd(const U32& a, const U32& b) { |
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h index 33bf2a7d0..6e29bf0e2 100644 --- a/src/shader_recompiler/frontend/ir/ir_emitter.h +++ b/src/shader_recompiler/frontend/ir/ir_emitter.h | |||
| @@ -150,9 +150,9 @@ public: | |||
| 150 | [[nodiscard]] U32 IMul(const U32& a, const U32& b); | 150 | [[nodiscard]] U32 IMul(const U32& a, const U32& b); |
| 151 | [[nodiscard]] U32U64 INeg(const U32U64& value); | 151 | [[nodiscard]] U32U64 INeg(const U32U64& value); |
| 152 | [[nodiscard]] U32 IAbs(const U32& value); | 152 | [[nodiscard]] U32 IAbs(const U32& value); |
| 153 | [[nodiscard]] U32 ShiftLeftLogical(const U32& base, const U32& shift); | 153 | [[nodiscard]] U32U64 ShiftLeftLogical(const U32U64& base, const U32& shift); |
| 154 | [[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift); | 154 | [[nodiscard]] U32U64 ShiftRightLogical(const U32U64& base, const U32& shift); |
| 155 | [[nodiscard]] U32 ShiftRightArithmetic(const U32& base, const U32& shift); | 155 | [[nodiscard]] U32U64 ShiftRightArithmetic(const U32U64& base, const U32& shift); |
| 156 | [[nodiscard]] U32 BitwiseAnd(const U32& a, const U32& b); | 156 | [[nodiscard]] U32 BitwiseAnd(const U32& a, const U32& b); |
| 157 | [[nodiscard]] U32 BitwiseOr(const U32& a, const U32& b); | 157 | [[nodiscard]] U32 BitwiseOr(const U32& a, const U32& b); |
| 158 | [[nodiscard]] U32 BitwiseXor(const U32& a, const U32& b); | 158 | [[nodiscard]] U32 BitwiseXor(const U32& a, const U32& b); |
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc index b51aaaef5..75f09ebfc 100644 --- a/src/shader_recompiler/frontend/ir/opcodes.inc +++ b/src/shader_recompiler/frontend/ir/opcodes.inc | |||
| @@ -236,9 +236,11 @@ OPCODE(INeg32, U32, U32, | |||
| 236 | OPCODE(INeg64, U64, U64, ) | 236 | OPCODE(INeg64, U64, U64, ) |
| 237 | OPCODE(IAbs32, U32, U32, ) | 237 | OPCODE(IAbs32, U32, U32, ) |
| 238 | OPCODE(ShiftLeftLogical32, U32, U32, U32, ) | 238 | OPCODE(ShiftLeftLogical32, U32, U32, U32, ) |
| 239 | OPCODE(ShiftLeftLogical64, U64, U64, U32, ) | ||
| 239 | OPCODE(ShiftRightLogical32, U32, U32, U32, ) | 240 | OPCODE(ShiftRightLogical32, U32, U32, U32, ) |
| 240 | OPCODE(ShiftRightLogical64, U64, U64, U32, ) | 241 | OPCODE(ShiftRightLogical64, U64, U64, U32, ) |
| 241 | OPCODE(ShiftRightArithmetic32, U32, U32, U32, ) | 242 | OPCODE(ShiftRightArithmetic32, U32, U32, U32, ) |
| 243 | OPCODE(ShiftRightArithmetic64, U64, U64, U32, ) | ||
| 242 | OPCODE(BitwiseAnd32, U32, U32, U32, ) | 244 | OPCODE(BitwiseAnd32, U32, U32, U32, ) |
| 243 | OPCODE(BitwiseOr32, U32, U32, U32, ) | 245 | OPCODE(BitwiseOr32, U32, U32, U32, ) |
| 244 | OPCODE(BitwiseXor32, U32, U32, U32, ) | 246 | OPCODE(BitwiseXor32, U32, U32, U32, ) |