summaryrefslogtreecommitdiff
path: root/src/shader_recompiler/frontend/ir
diff options
context:
space:
mode:
authorGravatar ameerj2021-03-07 22:01:22 -0500
committerGravatar ameerj2021-07-22 21:51:23 -0400
commit7d6ba5b9840a4ba00a9b0f207c1c119d60dcf8b7 (patch)
treed2e7976c767b5b292f0a0318783869045ff0fda6 /src/shader_recompiler/frontend/ir
parentshader: Implement SHF (diff)
downloadyuzu-7d6ba5b9840a4ba00a9b0f207c1c119d60dcf8b7.tar.gz
yuzu-7d6ba5b9840a4ba00a9b0f207c1c119d60dcf8b7.tar.xz
yuzu-7d6ba5b9840a4ba00a9b0f207c1c119d60dcf8b7.zip
shader: Implement R2P
Diffstat (limited to 'src/shader_recompiler/frontend/ir')
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.cpp2
-rw-r--r--src/shader_recompiler/frontend/ir/opcodes.inc1
2 files changed, 3 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index 1659b7f3b..f38b46bac 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -412,6 +412,8 @@ Value IREmitter::Select(const U1& condition, const Value& true_value, const Valu
412 throw InvalidArgument("Mismatching types {} and {}", true_value.Type(), false_value.Type()); 412 throw InvalidArgument("Mismatching types {} and {}", true_value.Type(), false_value.Type());
413 } 413 }
414 switch (true_value.Type()) { 414 switch (true_value.Type()) {
415 case Type::U1:
416 return Inst(Opcode::SelectU1, condition, true_value, false_value);
415 case Type::U8: 417 case Type::U8:
416 return Inst(Opcode::SelectU8, condition, true_value, false_value); 418 return Inst(Opcode::SelectU8, condition, true_value, false_value);
417 case Type::U16: 419 case Type::U16:
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc
index 75f09ebfc..c4e72c84d 100644
--- a/src/shader_recompiler/frontend/ir/opcodes.inc
+++ b/src/shader_recompiler/frontend/ir/opcodes.inc
@@ -115,6 +115,7 @@ OPCODE(CompositeInsertF64x3, F64x3, F64x
115OPCODE(CompositeInsertF64x4, F64x4, F64x4, F64, U32, ) 115OPCODE(CompositeInsertF64x4, F64x4, F64x4, F64, U32, )
116 116
117// Select operations 117// Select operations
118OPCODE(SelectU1, U1, U1, U1, U1, )
118OPCODE(SelectU8, U8, U1, U8, U8, ) 119OPCODE(SelectU8, U8, U1, U8, U8, )
119OPCODE(SelectU16, U16, U1, U16, U16, ) 120OPCODE(SelectU16, U16, U1, U16, U16, )
120OPCODE(SelectU32, U32, U1, U32, U32, ) 121OPCODE(SelectU32, U32, U1, U32, U32, )