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authorGravatar ReinUsesLisp2021-04-12 03:48:15 -0300
committerGravatar ameerj2021-07-22 21:51:27 -0400
commita6cef71cc0b03f929f1bc97152b302562f46bc53 (patch)
treeb6be5bddb79c93233f6081a930634345c353dec2 /src/shader_recompiler/frontend/ir
parentinternal_stage_buffer_entry_read: Remove pragma optimize off (diff)
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shader: Implement OUT
Diffstat (limited to '')
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.cpp8
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.h3
-rw-r--r--src/shader_recompiler/frontend/ir/microinstruction.cpp2
-rw-r--r--src/shader_recompiler/frontend/ir/opcodes.inc2
4 files changed, 15 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index 54a273a92..7d48fa1ba 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -125,6 +125,14 @@ void IREmitter::Epilogue() {
125 Inst(Opcode::Epilogue); 125 Inst(Opcode::Epilogue);
126} 126}
127 127
128void IREmitter::EmitVertex(const U32& stream) {
129 Inst(Opcode::EmitVertex, stream);
130}
131
132void IREmitter::EndPrimitive(const U32& stream) {
133 Inst(Opcode::EndPrimitive, stream);
134}
135
128U32 IREmitter::GetReg(IR::Reg reg) { 136U32 IREmitter::GetReg(IR::Reg reg) {
129 return Inst<U32>(Opcode::GetRegister, reg); 137 return Inst<U32>(Opcode::GetRegister, reg);
130} 138}
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h
index d04224707..033c4332e 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.h
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.h
@@ -43,6 +43,9 @@ public:
43 void Prologue(); 43 void Prologue();
44 void Epilogue(); 44 void Epilogue();
45 45
46 void EmitVertex(const U32& stream);
47 void EndPrimitive(const U32& stream);
48
46 [[nodiscard]] U32 GetReg(IR::Reg reg); 49 [[nodiscard]] U32 GetReg(IR::Reg reg);
47 void SetReg(IR::Reg reg, const U32& value); 50 void SetReg(IR::Reg reg, const U32& value);
48 51
diff --git a/src/shader_recompiler/frontend/ir/microinstruction.cpp b/src/shader_recompiler/frontend/ir/microinstruction.cpp
index 0f66c5627..204c55fa8 100644
--- a/src/shader_recompiler/frontend/ir/microinstruction.cpp
+++ b/src/shader_recompiler/frontend/ir/microinstruction.cpp
@@ -69,6 +69,8 @@ bool Inst::MayHaveSideEffects() const noexcept {
69 case Opcode::MemoryBarrierSystemLevel: 69 case Opcode::MemoryBarrierSystemLevel:
70 case Opcode::Prologue: 70 case Opcode::Prologue:
71 case Opcode::Epilogue: 71 case Opcode::Epilogue:
72 case Opcode::EmitVertex:
73 case Opcode::EndPrimitive:
72 case Opcode::SetAttribute: 74 case Opcode::SetAttribute:
73 case Opcode::SetAttributeIndexed: 75 case Opcode::SetAttributeIndexed:
74 case Opcode::SetFragColor: 76 case Opcode::SetFragColor:
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc
index f70008682..0e487f1a7 100644
--- a/src/shader_recompiler/frontend/ir/opcodes.inc
+++ b/src/shader_recompiler/frontend/ir/opcodes.inc
@@ -25,6 +25,8 @@ OPCODE(MemoryBarrierSystemLevel, Void,
25// Special operations 25// Special operations
26OPCODE(Prologue, Void, ) 26OPCODE(Prologue, Void, )
27OPCODE(Epilogue, Void, ) 27OPCODE(Epilogue, Void, )
28OPCODE(EmitVertex, Void, U32, )
29OPCODE(EndPrimitive, Void, U32, )
28 30
29// Context getters/setters 31// Context getters/setters
30OPCODE(GetRegister, U32, Reg, ) 32OPCODE(GetRegister, U32, Reg, )