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| author |  ameerj | 2021-03-10 22:42:17 -0500 |
|---|---|---|
| committer | ameerj | 2021-07-22 21:51:23 -0400 |
| commit | ba8c1d2eb479d04b2b0d847efd67468b688765d4 (patch) | |
| tree | c92c17f08ed3b313bbdb66917767ef8074d43c92 /src/shader_recompiler/frontend/ir/opcodes.inc | |
| parent | shader: Partial implementation of LDC (diff) | |
| download | yuzu-ba8c1d2eb479d04b2b0d847efd67468b688765d4.tar.gz yuzu-ba8c1d2eb479d04b2b0d847efd67468b688765d4.tar.xz yuzu-ba8c1d2eb479d04b2b0d847efd67468b688765d4.zip | |
shader: Implement FCMP
still need to configure some settings for NV denorm flush and intel NaN
Diffstat (limited to 'src/shader_recompiler/frontend/ir/opcodes.inc')
| -rw-r--r-- | src/shader_recompiler/frontend/ir/opcodes.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc index 64bd495ed..476281789 100644 --- a/src/shader_recompiler/frontend/ir/opcodes.inc +++ b/src/shader_recompiler/frontend/ir/opcodes.inc | |||
| @@ -197,6 +197,7 @@ OPCODE(FPTrunc16, F16, F16, | |||
| 197 | OPCODE(FPTrunc32, F32, F32, ) | 197 | OPCODE(FPTrunc32, F32, F32, ) |
| 198 | OPCODE(FPTrunc64, F64, F64, ) | 198 | OPCODE(FPTrunc64, F64, F64, ) |
| 199 | 199 | ||
| 200 | <<<<<<< HEAD | ||
| 200 | OPCODE(FPOrdEqual16, U1, F16, F16, ) | 201 | OPCODE(FPOrdEqual16, U1, F16, F16, ) |
| 201 | OPCODE(FPOrdEqual32, U1, F32, F32, ) | 202 | OPCODE(FPOrdEqual32, U1, F32, F32, ) |
| 202 | OPCODE(FPOrdEqual64, U1, F64, F64, ) | 203 | OPCODE(FPOrdEqual64, U1, F64, F64, ) |
| @@ -233,6 +234,7 @@ OPCODE(FPOrdGreaterThanEqual64, U1, F64, | |||
| 233 | OPCODE(FPUnordGreaterThanEqual16, U1, F16, F16, ) | 234 | OPCODE(FPUnordGreaterThanEqual16, U1, F16, F16, ) |
| 234 | OPCODE(FPUnordGreaterThanEqual32, U1, F32, F32, ) | 235 | OPCODE(FPUnordGreaterThanEqual32, U1, F32, F32, ) |
| 235 | OPCODE(FPUnordGreaterThanEqual64, U1, F64, F64, ) | 236 | OPCODE(FPUnordGreaterThanEqual64, U1, F64, F64, ) |
| 237 | OPCODE(FPIsNan32, U1, F32, ) | ||
| 236 | 238 | ||
| 237 | // Integer operations | 239 | // Integer operations |
| 238 | OPCODE(IAdd32, U32, U32, U32, ) | 240 | OPCODE(IAdd32, U32, U32, U32, ) |