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| author | 2021-02-11 16:39:06 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:22 -0400 | |
| commit | 9170200a11715d131645d1ffb92e86e6ef0d7e88 (patch) | |
| tree | 6c6f84c38a9b59d023ecb09c0737ea56da166b64 /src/shader_recompiler/frontend/ir/microinstruction.cpp | |
| parent | spirv: Initial SPIR-V support (diff) | |
| download | yuzu-9170200a11715d131645d1ffb92e86e6ef0d7e88.tar.gz yuzu-9170200a11715d131645d1ffb92e86e6ef0d7e88.tar.xz yuzu-9170200a11715d131645d1ffb92e86e6ef0d7e88.zip | |
shader: Initial implementation of an AST
Diffstat (limited to '')
| -rw-r--r-- | src/shader_recompiler/frontend/ir/microinstruction.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/shader_recompiler/frontend/ir/microinstruction.cpp b/src/shader_recompiler/frontend/ir/microinstruction.cpp index e7ca92039..b4ae371bd 100644 --- a/src/shader_recompiler/frontend/ir/microinstruction.cpp +++ b/src/shader_recompiler/frontend/ir/microinstruction.cpp | |||
| @@ -51,9 +51,9 @@ bool Inst::MayHaveSideEffects() const noexcept { | |||
| 51 | switch (op) { | 51 | switch (op) { |
| 52 | case Opcode::Branch: | 52 | case Opcode::Branch: |
| 53 | case Opcode::BranchConditional: | 53 | case Opcode::BranchConditional: |
| 54 | case Opcode::Exit: | 54 | case Opcode::LoopMerge: |
| 55 | case Opcode::SelectionMerge: | ||
| 55 | case Opcode::Return: | 56 | case Opcode::Return: |
| 56 | case Opcode::Unreachable: | ||
| 57 | case Opcode::SetAttribute: | 57 | case Opcode::SetAttribute: |
| 58 | case Opcode::SetAttributeIndexed: | 58 | case Opcode::SetAttributeIndexed: |
| 59 | case Opcode::WriteGlobalU8: | 59 | case Opcode::WriteGlobalU8: |