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| author | 2021-04-01 22:20:57 +0200 | |
|---|---|---|
| committer | 2021-07-22 21:51:25 -0400 | |
| commit | ecb30c907266921818d5b6b03e341028fa2ea082 (patch) | |
| tree | 8bf3f0097653fa11b6dae823f79fe671204ad55e /src/shader_recompiler/frontend/ir/ir_emitter.cpp | |
| parent | shader: Mark SSBOs as written when they are (diff) | |
| download | yuzu-ecb30c907266921818d5b6b03e341028fa2ea082.tar.gz yuzu-ecb30c907266921818d5b6b03e341028fa2ea082.tar.xz yuzu-ecb30c907266921818d5b6b03e341028fa2ea082.zip | |
shader: Improve VOTE.VTG stub
Diffstat (limited to 'src/shader_recompiler/frontend/ir/ir_emitter.cpp')
| -rw-r--r-- | src/shader_recompiler/frontend/ir/ir_emitter.cpp | 37 |
1 files changed, 35 insertions, 2 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp index 5258ede09..ddaa873f2 100644 --- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp +++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp | |||
| @@ -198,6 +198,38 @@ void IREmitter::SetOFlag(const U1& value) { | |||
| 198 | Inst(Opcode::SetOFlag, value); | 198 | Inst(Opcode::SetOFlag, value); |
| 199 | } | 199 | } |
| 200 | 200 | ||
| 201 | U1 IREmitter::GetFCSMFlag() { | ||
| 202 | return Inst<U1>(Opcode::GetFCSMFlag); | ||
| 203 | } | ||
| 204 | |||
| 205 | U1 IREmitter::GetTAFlag() { | ||
| 206 | return Inst<U1>(Opcode::GetTAFlag); | ||
| 207 | } | ||
| 208 | |||
| 209 | U1 IREmitter::GetTRFlag() { | ||
| 210 | return Inst<U1>(Opcode::GetTRFlag); | ||
| 211 | } | ||
| 212 | |||
| 213 | U1 IREmitter::GetMXFlag() { | ||
| 214 | return Inst<U1>(Opcode::GetMXFlag); | ||
| 215 | } | ||
| 216 | |||
| 217 | void IREmitter::SetFCSMFlag(const U1& value) { | ||
| 218 | Inst(Opcode::SetFCSMFlag, value); | ||
| 219 | } | ||
| 220 | |||
| 221 | void IREmitter::SetTAFlag(const U1& value) { | ||
| 222 | Inst(Opcode::SetTAFlag, value); | ||
| 223 | } | ||
| 224 | |||
| 225 | void IREmitter::SetTRFlag(const U1& value) { | ||
| 226 | Inst(Opcode::SetTRFlag, value); | ||
| 227 | } | ||
| 228 | |||
| 229 | void IREmitter::SetMXFlag(const U1& value) { | ||
| 230 | Inst(Opcode::SetMXFlag, value); | ||
| 231 | } | ||
| 232 | |||
| 201 | static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) { | 233 | static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) { |
| 202 | switch (flow_test) { | 234 | switch (flow_test) { |
| 203 | case FlowTest::F: | 235 | case FlowTest::F: |
| @@ -256,13 +288,14 @@ static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) { | |||
| 256 | return ir.LogicalOr(ir.GetSFlag(), ir.GetZFlag()); | 288 | return ir.LogicalOr(ir.GetSFlag(), ir.GetZFlag()); |
| 257 | case FlowTest::RGT: | 289 | case FlowTest::RGT: |
| 258 | return ir.LogicalAnd(ir.LogicalNot(ir.GetSFlag()), ir.LogicalNot(ir.GetZFlag())); | 290 | return ir.LogicalAnd(ir.LogicalNot(ir.GetSFlag()), ir.LogicalNot(ir.GetZFlag())); |
| 291 | |||
| 292 | case FlowTest::FCSM_TR: | ||
| 293 | return ir.LogicalAnd(ir.GetFCSMFlag(), ir.GetTRFlag()); | ||
| 259 | case FlowTest::CSM_TA: | 294 | case FlowTest::CSM_TA: |
| 260 | case FlowTest::CSM_TR: | 295 | case FlowTest::CSM_TR: |
| 261 | case FlowTest::CSM_MX: | 296 | case FlowTest::CSM_MX: |
| 262 | case FlowTest::FCSM_TA: | 297 | case FlowTest::FCSM_TA: |
| 263 | case FlowTest::FCSM_TR: | ||
| 264 | case FlowTest::FCSM_MX: | 298 | case FlowTest::FCSM_MX: |
| 265 | return ir.Imm1(false); | ||
| 266 | default: | 299 | default: |
| 267 | throw NotImplementedException("Flow test {}", flow_test); | 300 | throw NotImplementedException("Flow test {}", flow_test); |
| 268 | } | 301 | } |