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| author | 2021-04-04 05:17:17 -0300 | |
|---|---|---|
| committer | 2021-07-22 21:51:26 -0400 | |
| commit | da6cf2632cd4dc0d2b0278353fcaee0789b418c0 (patch) | |
| tree | 90c2d6f6fa724365a4a23c888389e525e316a4fd /src/shader_recompiler/frontend/ir/ir_emitter.cpp | |
| parent | shader: Implement BAR and fix memory barriers (diff) | |
| download | yuzu-da6cf2632cd4dc0d2b0278353fcaee0789b418c0.tar.gz yuzu-da6cf2632cd4dc0d2b0278353fcaee0789b418c0.tar.xz yuzu-da6cf2632cd4dc0d2b0278353fcaee0789b418c0.zip | |
shader: Add subgroup masks
Diffstat (limited to 'src/shader_recompiler/frontend/ir/ir_emitter.cpp')
| -rw-r--r-- | src/shader_recompiler/frontend/ir/ir_emitter.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp index 246c3b9ef..ed1e0dd3b 100644 --- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp +++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp | |||
| @@ -1628,6 +1628,26 @@ U32 IREmitter::SubgroupBallot(const U1& value) { | |||
| 1628 | return Inst<U32>(Opcode::SubgroupBallot, value); | 1628 | return Inst<U32>(Opcode::SubgroupBallot, value); |
| 1629 | } | 1629 | } |
| 1630 | 1630 | ||
| 1631 | U32 IREmitter::SubgroupEqMask() { | ||
| 1632 | return Inst<U32>(Opcode::SubgroupEqMask); | ||
| 1633 | } | ||
| 1634 | |||
| 1635 | U32 IREmitter::SubgroupLtMask() { | ||
| 1636 | return Inst<U32>(Opcode::SubgroupLtMask); | ||
| 1637 | } | ||
| 1638 | |||
| 1639 | U32 IREmitter::SubgroupLeMask() { | ||
| 1640 | return Inst<U32>(Opcode::SubgroupLeMask); | ||
| 1641 | } | ||
| 1642 | |||
| 1643 | U32 IREmitter::SubgroupGtMask() { | ||
| 1644 | return Inst<U32>(Opcode::SubgroupGtMask); | ||
| 1645 | } | ||
| 1646 | |||
| 1647 | U32 IREmitter::SubgroupGeMask() { | ||
| 1648 | return Inst<U32>(Opcode::SubgroupGeMask); | ||
| 1649 | } | ||
| 1650 | |||
| 1631 | U32 IREmitter::ShuffleIndex(const IR::U32& value, const IR::U32& index, const IR::U32& clamp, | 1651 | U32 IREmitter::ShuffleIndex(const IR::U32& value, const IR::U32& index, const IR::U32& clamp, |
| 1632 | const IR::U32& seg_mask) { | 1652 | const IR::U32& seg_mask) { |
| 1633 | return Inst<U32>(Opcode::ShuffleIndex, value, index, clamp, seg_mask); | 1653 | return Inst<U32>(Opcode::ShuffleIndex, value, index, clamp, seg_mask); |