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authorGravatar ReinUsesLisp2021-05-14 00:40:54 -0300
committerGravatar ameerj2021-07-22 21:51:31 -0400
commitd54d7de40e7295827b0e4e4026441b53d3fc9569 (patch)
tree29b5074f851292dace7aeb5da7716675544b3735 /src/shader_recompiler/frontend/ir/ir_emitter.cpp
parentglasm: Implement Storage atomics (diff)
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glasm: Rework control flow introducing a syntax list
This commit regresses VertexA shaders, their transformation pass has to be adapted to the new control flow.
Diffstat (limited to 'src/shader_recompiler/frontend/ir/ir_emitter.cpp')
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.cpp60
1 files changed, 16 insertions, 44 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index ce6c9af07..eb45aa477 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -61,25 +61,28 @@ F64 IREmitter::Imm64(f64 value) const {
61 return F64{Value{value}}; 61 return F64{Value{value}};
62} 62}
63 63
64void IREmitter::Branch(Block* label) { 64void IREmitter::Prologue() {
65 label->AddImmediatePredecessor(block); 65 Inst(Opcode::Prologue);
66 block->SetBranch(label);
67 Inst(Opcode::Branch, label);
68} 66}
69 67
70void IREmitter::BranchConditional(const U1& condition, Block* true_label, Block* false_label) { 68void IREmitter::Epilogue() {
71 block->SetBranches(IR::Condition{true}, true_label, false_label); 69 Inst(Opcode::Epilogue);
72 true_label->AddImmediatePredecessor(block);
73 false_label->AddImmediatePredecessor(block);
74 Inst(Opcode::BranchConditional, condition, true_label, false_label);
75} 70}
76 71
77void IREmitter::LoopMerge(Block* merge_block, Block* continue_target) { 72void IREmitter::BranchConditionRef(const U1& cond) {
78 Inst(Opcode::LoopMerge, merge_block, continue_target); 73 Inst(Opcode::BranchConditionRef, cond);
79} 74}
80 75
81void IREmitter::SelectionMerge(Block* merge_block) { 76void IREmitter::DemoteToHelperInvocation() {
82 Inst(Opcode::SelectionMerge, merge_block); 77 Inst(Opcode::DemoteToHelperInvocation);
78}
79
80void IREmitter::EmitVertex(const U32& stream) {
81 Inst(Opcode::EmitVertex, stream);
82}
83
84void IREmitter::EndPrimitive(const U32& stream) {
85 Inst(Opcode::EndPrimitive, stream);
83} 86}
84 87
85void IREmitter::Barrier() { 88void IREmitter::Barrier() {
@@ -94,37 +97,6 @@ void IREmitter::DeviceMemoryBarrier() {
94 Inst(Opcode::DeviceMemoryBarrier); 97 Inst(Opcode::DeviceMemoryBarrier);
95} 98}
96 99
97void IREmitter::Return() {
98 block->SetReturn();
99 Inst(Opcode::Return);
100}
101
102void IREmitter::Unreachable() {
103 Inst(Opcode::Unreachable);
104}
105
106void IREmitter::DemoteToHelperInvocation(Block* continue_label) {
107 block->SetBranch(continue_label);
108 continue_label->AddImmediatePredecessor(block);
109 Inst(Opcode::DemoteToHelperInvocation, continue_label);
110}
111
112void IREmitter::Prologue() {
113 Inst(Opcode::Prologue);
114}
115
116void IREmitter::Epilogue() {
117 Inst(Opcode::Epilogue);
118}
119
120void IREmitter::EmitVertex(const U32& stream) {
121 Inst(Opcode::EmitVertex, stream);
122}
123
124void IREmitter::EndPrimitive(const U32& stream) {
125 Inst(Opcode::EndPrimitive, stream);
126}
127
128U32 IREmitter::GetReg(IR::Reg reg) { 100U32 IREmitter::GetReg(IR::Reg reg) {
129 return Inst<U32>(Opcode::GetRegister, reg); 101 return Inst<U32>(Opcode::GetRegister, reg);
130} 102}