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authorGravatar FernandoS272021-04-03 01:48:39 +0200
committerGravatar ameerj2021-07-22 21:51:26 -0400
commitbaec84247fe815199595d9e8077b71f3b5c8317e (patch)
tree84195625ffb43922ba87b25296057bdeb9f22a2c /src/shader_recompiler/frontend/ir/ir_emitter.cpp
parentshader: Implement SR_LaneId (diff)
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shader: Address Feedback
Diffstat (limited to 'src/shader_recompiler/frontend/ir/ir_emitter.cpp')
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.cpp49
1 files changed, 13 insertions, 36 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index b5f61956a..5e94edd74 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -82,8 +82,17 @@ void IREmitter::SelectionMerge(Block* merge_block) {
82 Inst(Opcode::SelectionMerge, merge_block); 82 Inst(Opcode::SelectionMerge, merge_block);
83} 83}
84 84
85void IREmitter::MemoryBarrier(BarrierInstInfo info) { 85void IREmitter::MemoryBarrier(MemoryScope scope) {
86 Inst(Opcode::MemoryBarrier, Flags{info}); 86 switch (scope) {
87 case MemoryScope::Workgroup:
88 Inst(Opcode::MemoryBarrierWorkgroupLevel);
89 case MemoryScope::Device:
90 Inst(Opcode::MemoryBarrierDeviceLevel);
91 case MemoryScope::System:
92 Inst(Opcode::MemoryBarrierSystemLevel);
93 default:
94 throw InvalidArgument("Invalid memory scope {}", scope);
95 }
87} 96}
88 97
89void IREmitter::Return() { 98void IREmitter::Return() {
@@ -202,38 +211,6 @@ void IREmitter::SetOFlag(const U1& value) {
202 Inst(Opcode::SetOFlag, value); 211 Inst(Opcode::SetOFlag, value);
203} 212}
204 213
205U1 IREmitter::GetFCSMFlag() {
206 return Inst<U1>(Opcode::GetFCSMFlag);
207}
208
209U1 IREmitter::GetTAFlag() {
210 return Inst<U1>(Opcode::GetTAFlag);
211}
212
213U1 IREmitter::GetTRFlag() {
214 return Inst<U1>(Opcode::GetTRFlag);
215}
216
217U1 IREmitter::GetMXFlag() {
218 return Inst<U1>(Opcode::GetMXFlag);
219}
220
221void IREmitter::SetFCSMFlag(const U1& value) {
222 Inst(Opcode::SetFCSMFlag, value);
223}
224
225void IREmitter::SetTAFlag(const U1& value) {
226 Inst(Opcode::SetTAFlag, value);
227}
228
229void IREmitter::SetTRFlag(const U1& value) {
230 Inst(Opcode::SetTRFlag, value);
231}
232
233void IREmitter::SetMXFlag(const U1& value) {
234 Inst(Opcode::SetMXFlag, value);
235}
236
237static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) { 214static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) {
238 switch (flow_test) { 215 switch (flow_test) {
239 case FlowTest::F: 216 case FlowTest::F:
@@ -292,9 +269,9 @@ static U1 GetFlowTest(IREmitter& ir, FlowTest flow_test) {
292 return ir.LogicalOr(ir.GetSFlag(), ir.GetZFlag()); 269 return ir.LogicalOr(ir.GetSFlag(), ir.GetZFlag());
293 case FlowTest::RGT: 270 case FlowTest::RGT:
294 return ir.LogicalAnd(ir.LogicalNot(ir.GetSFlag()), ir.LogicalNot(ir.GetZFlag())); 271 return ir.LogicalAnd(ir.LogicalNot(ir.GetSFlag()), ir.LogicalNot(ir.GetZFlag()));
295
296 case FlowTest::FCSM_TR: 272 case FlowTest::FCSM_TR:
297 return ir.LogicalAnd(ir.GetFCSMFlag(), ir.GetTRFlag()); 273 // LOG_WARNING(ShaderDecompiler, "FCSM_TR CC State (Stubbed)");
274 return ir.Imm1(false);
298 case FlowTest::CSM_TA: 275 case FlowTest::CSM_TA:
299 case FlowTest::CSM_TR: 276 case FlowTest::CSM_TR:
300 case FlowTest::CSM_MX: 277 case FlowTest::CSM_MX: